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nvethernet: Move nvidia,vm-irq-config to overlay

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Move nvidia,vm-irq-config to overlay from Base
DT to overlay DT

Bug 3956724

Change-Id: Ib6c8f1af7aa5ccb6de8c19c1ae721d2ccd79f01e
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x-generic-dts/+/2855643
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Revanth Kumar Uppala
2023-02-09 05:50:20 +00:00
committed by Laxman Dewangan
parent a03f88c36e
commit 7dba78d931
2 changed files with 35 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
overlay/tegra234-soc-overlay.dtsi
View File

@@ -564,6 +564,7 @@
interconnect-names = "dma-mem", "write"; interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
nvidia,vm-irq-config = <&mgbe_vm_irq_config>;
nvidia,num-dma-chans = <10>; nvidia,num-dma-chans = <10>;
nvidia,dma-chans = <0 1 2 3 4 5 6 7 8 9>; nvidia,dma-chans = <0 1 2 3 4 5 6 7 8 9>;
nvidia,num-mtl-queues = <10>; nvidia,num-mtl-queues = <10>;
@@ -995,6 +996,40 @@
fragment-t234@2 { fragment-t234@2 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
mgbe_vm_irq_config: mgbe-vm-irq-config {
nvidia,num-vm-irqs = <5>;
vm_irq1 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <0 1>;
nvidia,vm-num = <0>;
nvidia,vm-irq-id = <0>;
};
vm_irq2 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <2 3>;
nvidia,vm-num = <1>;
nvidia,vm-irq-id = <1>;
};
vm_irq3 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <4 5>;
nvidia,vm-num = <2>;
nvidia,vm-irq-id = <2>;
};
vm_irq4 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <6 7>;
nvidia,vm-num = <3>;
nvidia,vm-irq-id = <3>;
};
vm_irq5 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <8 9>;
nvidia,vm-num = <4>;
nvidia,vm-irq-id = <4>;
};
};
aliases { aliases {
serial1 = "/bus@0/serial@3110000"; serial1 = "/bus@0/serial@3110000";
i2c0 = "/bus@0/i2c@3160000"; i2c0 = "/bus@0/i2c@3160000";

30
tegra234.dtsi
View File

@@ -998,7 +998,6 @@
interconnect-names = "dma-mem", "write"; interconnect-names = "dma-mem", "write";
iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
nvidia,vm-irq-config = <&mgbe_vm_irq_config>;
status = "disabled"; status = "disabled";
}; };
@@ -1104,35 +1103,6 @@
status = "disabled"; status = "disabled";
}; };
mgbe_vm_irq_config: mgbe-vm-irq-config {
nvidia,num-vm-irqs = <5>;
vm_irq1 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <0 1>;
nvidia,vm-num = <0>;
};
vm_irq2 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <2 3>;
nvidia,vm-num = <1>;
};
vm_irq3 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <4 5>;
nvidia,vm-num = <2>;
};
vm_irq4 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <6 7>;
nvidia,vm-num = <3>;
};
vm_irq5 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <8 9>;
nvidia,vm-num = <4>;
};
};
smmu_niso1: iommu@8000000 { smmu_niso1: iommu@8000000 {
compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
reg = <0x8000000 0x1000000>, reg = <0x8000000 0x1000000>,