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tegra234: Set audio-hub clock parent as PLLP

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Set the audio-bub parent clock as PLLP instead of PLLA
to align the configuration to mainline 6.5.rc2.

Bug 4037899

Change-Id: Icbbcb7e22a5ef63701b507ad53bd53f83f063fed
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2948444
(cherry picked from commit 8e955b03dd)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2955404
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Laxman Dewangan
2023-08-04 05:20:58 +00:00
committed by mobile promotions
parent aba3fe360c
commit 8b15f87dc5
1 changed files with 2 additions and 1 deletions
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tegra234.dtsi
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@@ -180,7 +180,8 @@
clocks = <&bpmp TEGRA234_CLK_AHUB>; clocks = <&bpmp TEGRA234_CLK_AHUB>;
clock-names = "ahub"; clock-names = "ahub";
assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clock-rates = <81600000>;
status = "disabled"; status = "disabled";
#address-cells = <2>; #address-cells = <2>;