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nv-public: remove REMOVE_FRAGMENT_SYNTAX

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These preprocessor conditionals were a temporary step to facilitate
step by step reviews.  Remove them and fix indentation.

Bug 4290389

Change-Id: Iecdbdf1869bec00538530d59420622d8563a116a
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3000004
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Gautham Srinivasan <gauthams@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Brad Griffis
2023-10-19 00:50:10 +00:00
committed by mobile promotions
parent ff77a8a1cd
commit 8f0cbdad83
35 changed files with 8784 additions and 9020 deletions
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1472
nv-soc/tegra234-base-overlay.dtsi
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4533
nv-soc/tegra234-soc-audio-dai-links.dtsi
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479
nv-soc/tegra234-soc-camera.dtsi
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@@ -12,262 +12,253 @@
#include <dt-bindings/memory/tegra234-mc.h>
/ {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-camera@0 {
target-path = "/";
__overlay__ {
#endif
aliases { /* RCE is the Camera RTCPU */
tegra-camera-rtcpu = "/rtcpu@bc00000";
};
aliases { /* RCE is the Camera RTCPU */
tegra-camera-rtcpu = "/rtcpu@bc00000";
};
bus@0 {
host1x@13e00000 {
vi0: vi0@15c00000 {
compatible = "nvidia,tegra234-vi";
clocks = <&bpmp TEGRA234_CLK_VI>;
clock-names = "vi";
nvidia,vi-falcon-device = <&vi0_thi>;
resets = <&bpmp TEGRA234_RESET_VI>;
reset-names = "vi0";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIW &emc>;
interconnect-names = "write";
non-coherent;
status = "okay";
};
vi0_thi: vi0-thi@15f00000 {
compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI>;
reset-names = "vi0_thi";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2FALR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_VI2FALW &emc>;
interconnect-names = "dma-mem", "write";
status = "okay";
};
vi1: vi1@14c00000 {
compatible = "nvidia,tegra234-vi";
clocks = <&bpmp TEGRA234_CLK_VI>;
clock-names = "vi";
nvidia,vi-falcon-device = <&vi1_thi>;
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI2>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2W &emc>;
interconnect-names = "write";
non-coherent;
status = "okay";
};
vi1_thi: vi1-thi@14f00000 {
compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1_thi";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIFALR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_VIFALW &emc>;
interconnect-names = "dma-mem", "write";
status = "okay";
};
isp: isp@14800000 {
compatible = "nvidia,tegra194-isp";
reg = <0x0 0x14800000 0x0 0x00010000>;
resets = <&bpmp TEGRA234_RESET_ISP>;
reset-names = "isp";
clocks = <&bpmp TEGRA234_CLK_ISP>;
clock-names = "isp";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_ISPA>;
nvidia,isp-falcon-device = <&isp_thi>;
iommus = <&smmu_niso1 TEGRA234_SID_ISP>;
dma-coherent;
status = "okay";
};
isp_thi: isp-thi@14b00000 {
compatible = "nvidia,tegra194-isp-thi";
resets = <&bpmp TEGRA234_RESET_ISP>;
status = "okay";
};
nvcsi: nvcsi@15a00000 {
compatible = "nvidia,tegra194-nvcsi";
resets = <&bpmp TEGRA234_RESET_NVCSI>;
reset-names = "nvcsi";
clocks = <&bpmp TEGRA234_CLK_NVCSI>;
clock-names = "nvcsi";
status = "okay";
};
};
};
tegra_rce: rtcpu@bc00000 {
compatible = "nvidia,tegra194-rce";
nvidia,cpu-name = "rce";
reg = <0 0xbc00000 0 0x1000>, /* RCE EVP (RCE_ATCM_EVP) */
<0 0xb9f0000 0 0x40000>, /* RCE PM */
<0 0xb840000 0 0x10000>,
<0 0xb850000 0 0x10000>;
reg-names = "rce-evp", "rce-pm",
"ast-cpu", "ast-dma";
clocks =
<&bpmp TEGRA234_CLK_RCE_CPU_NIC>,
<&bpmp TEGRA234_CLK_RCE_NIC>,
<&bpmp TEGRA234_CLK_RCE_CPU>;
clock-names = "rce-cpu-nic", "rce-nic", "rce-cpu";
nvidia,clock-rates =
<115200000 601600000>,
<115200000 601600000>,
<115200000 601600000>;
resets = <&bpmp TEGRA234_RESET_RCE_ALL>;
reset-names = "rce-all";
interrupts = <GIC_SPI TEGRA234_IRQ_RCE_WDT_REMOTE IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt-remote";
iommus = <&smmu_niso0 TEGRA234_SID_RCE>;
memory-region = <&rce_resv>;
dma-coherent;
/* Memory bandwidth in kB/s during boot */
nvidia,test-bw = <2400000>;
nvidia,trace = <&rtcpu_trace 4 0x70100000 0x100000>;
nvidia,ivc-channels = <&camera_ivc_channels 2 0x90000000 0x10000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_RCER &emc>,
<&mc TEGRA234_MEMORY_CLIENT_RCEW &emc>;
interconnect-names = "dma-mem", "write";
nvidia,autosuspend-delay-ms = <5000>;
bus@0 {
host1x@13e00000 {
vi0: vi0@15c00000 {
compatible = "nvidia,tegra234-vi";
clocks = <&bpmp TEGRA234_CLK_VI>;
clock-names = "vi";
nvidia,vi-falcon-device = <&vi0_thi>;
resets = <&bpmp TEGRA234_RESET_VI>;
reset-names = "vi0";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIW &emc>;
interconnect-names = "write";
non-coherent;
status = "okay";
hsp-vm1 {
compatible = "nvidia,tegra-camrtc-hsp-vm";
mboxes =
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(0)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(1)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 0>;
mbox-names = "vm-tx", "vm-rx", "vm-ss";
status = "okay";
};
hsp-vm2 {
compatible = "nvidia,tegra-camrtc-hsp-vm";
mboxes =
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(2)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(3)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 1>;
mbox-names = "vm-tx", "vm-rx", "vm-ss";
status = "disabled";
};
};
camera_ivc_channels: camera-ivc-channels {
echo@0 {
compatible = "nvidia,tegra186-camera-ivc-protocol-echo";
nvidia,service = "echo";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <16>;
nvidia,frame-size = <64>;
};
dbg@1 {
/* This is raw channel exposed as device */
compatible = "nvidia,tegra186-camera-ivc-protocol-dbg";
nvidia,service = "debug";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <448>;
};
dbg@2 {
/* This is exposed in debugfs */
compatible = "nvidia,tegra186-camera-ivc-protocol-debug";
nvidia,service = "debug";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <8192>;
nvidia,ivc-timeout = <50>;
nvidia,test-timeout = <5000>;
nvidia,mem-map = <&tegra_rce &vi0 &isp &vi1>;
/* Memory bandwidth in kB/s during tests */
nvidia,test-bw = <2400000>;
};
ivccontrol@3 {
compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control";
nvidia,service = "capture-control";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <64>;
nvidia,frame-size = <320>;
};
ivccapture@4 {
compatible = "nvidia,tegra186-camera-ivc-protocol-capture";
nvidia,service = "capture";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <512>;
nvidia,frame-size = <64>;
};
diag@5 {
compatible = "nvidia,tegra186-camera-diagnostics";
nvidia,service = "diag";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <64>;
};
vi0_thi: vi0-thi@15f00000 {
compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI>;
reset-names = "vi0_thi";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2FALR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_VI2FALW &emc>;
interconnect-names = "dma-mem", "write";
status = "okay";
};
rtcpu_trace: tegra-rtcpu-trace {
nvidia,enable-printk;
nvidia,interval-ms = <50>;
nvidia,log-prefix = "[RCE]";
vi1: vi1@14c00000 {
compatible = "nvidia,tegra234-vi";
clocks = <&bpmp TEGRA234_CLK_VI>;
clock-names = "vi";
nvidia,vi-falcon-device = <&vi1_thi>;
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI2>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2W &emc>;
interconnect-names = "write";
non-coherent;
status = "okay";
};
capture_vi: tegra-capture-vi {
compatible = "nvidia,tegra-camrtc-capture-vi";
nvidia,vi-devices = <&vi0 &vi1>;
nvidia,vi-mapping-size = <6>;
nvidia,vi-mapping =
<0 0>,
<1 0>,
<2 1>,
<3 1>,
<4 0>,
<5 1>;
nvidia,vi-mapping-names = "csi-stream-id", "vi-unit-id";
nvidia,vi-max-channels = <72>;
vi1_thi: vi1-thi@14f00000 {
compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1_thi";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIFALR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_VIFALW &emc>;
interconnect-names = "dma-mem", "write";
status = "okay";
};
reserved-memory {
rce_resv: rce-reservation {
iommu-addresses = <&tegra_rce 0x0 0x00000000 0x00000000 0xA0000000>,
<&tegra_rce 0x0 0xC0000000 0xffffffff 0x3fffffff>;
};
isp: isp@14800000 {
compatible = "nvidia,tegra194-isp";
reg = <0x0 0x14800000 0x0 0x00010000>;
camdbg_reserved: camdbg_carveout {
compatible = "nvidia,camdbg_carveout";
size = <0 0x3200000>;
alignment = <0 0x100000>;
alloc-ranges = <0x1 0 0x1 0>;
status = "disabled";
};
resets = <&bpmp TEGRA234_RESET_ISP>;
reset-names = "isp";
clocks = <&bpmp TEGRA234_CLK_ISP>;
clock-names = "isp";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_ISPA>;
nvidia,isp-falcon-device = <&isp_thi>;
iommus = <&smmu_niso1 TEGRA234_SID_ISP>;
dma-coherent;
status = "okay";
};
isp_thi: isp-thi@14b00000 {
compatible = "nvidia,tegra194-isp-thi";
resets = <&bpmp TEGRA234_RESET_ISP>;
status = "okay";
};
nvcsi: nvcsi@15a00000 {
compatible = "nvidia,tegra194-nvcsi";
resets = <&bpmp TEGRA234_RESET_NVCSI>;
reset-names = "nvcsi";
clocks = <&bpmp TEGRA234_CLK_NVCSI>;
clock-names = "nvcsi";
status = "okay";
};
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
tegra_rce: rtcpu@bc00000 {
compatible = "nvidia,tegra194-rce";
nvidia,cpu-name = "rce";
reg = <0 0xbc00000 0 0x1000>, /* RCE EVP (RCE_ATCM_EVP) */
<0 0xb9f0000 0 0x40000>, /* RCE PM */
<0 0xb840000 0 0x10000>,
<0 0xb850000 0 0x10000>;
reg-names = "rce-evp", "rce-pm",
"ast-cpu", "ast-dma";
clocks =
<&bpmp TEGRA234_CLK_RCE_CPU_NIC>,
<&bpmp TEGRA234_CLK_RCE_NIC>,
<&bpmp TEGRA234_CLK_RCE_CPU>;
clock-names = "rce-cpu-nic", "rce-nic", "rce-cpu";
nvidia,clock-rates =
<115200000 601600000>,
<115200000 601600000>,
<115200000 601600000>;
resets = <&bpmp TEGRA234_RESET_RCE_ALL>;
reset-names = "rce-all";
interrupts = <GIC_SPI TEGRA234_IRQ_RCE_WDT_REMOTE IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt-remote";
iommus = <&smmu_niso0 TEGRA234_SID_RCE>;
memory-region = <&rce_resv>;
dma-coherent;
/* Memory bandwidth in kB/s during boot */
nvidia,test-bw = <2400000>;
nvidia,trace = <&rtcpu_trace 4 0x70100000 0x100000>;
nvidia,ivc-channels = <&camera_ivc_channels 2 0x90000000 0x10000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_RCER &emc>,
<&mc TEGRA234_MEMORY_CLIENT_RCEW &emc>;
interconnect-names = "dma-mem", "write";
nvidia,autosuspend-delay-ms = <5000>;
status = "okay";
hsp-vm1 {
compatible = "nvidia,tegra-camrtc-hsp-vm";
mboxes =
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(0)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(1)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 0>;
mbox-names = "vm-tx", "vm-rx", "vm-ss";
status = "okay";
};
hsp-vm2 {
compatible = "nvidia,tegra-camrtc-hsp-vm";
mboxes =
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(2)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(3)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 1>;
mbox-names = "vm-tx", "vm-rx", "vm-ss";
status = "disabled";
};
};
camera_ivc_channels: camera-ivc-channels {
echo@0 {
compatible = "nvidia,tegra186-camera-ivc-protocol-echo";
nvidia,service = "echo";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <16>;
nvidia,frame-size = <64>;
};
dbg@1 {
/* This is raw channel exposed as device */
compatible = "nvidia,tegra186-camera-ivc-protocol-dbg";
nvidia,service = "debug";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <448>;
};
dbg@2 {
/* This is exposed in debugfs */
compatible = "nvidia,tegra186-camera-ivc-protocol-debug";
nvidia,service = "debug";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <8192>;
nvidia,ivc-timeout = <50>;
nvidia,test-timeout = <5000>;
nvidia,mem-map = <&tegra_rce &vi0 &isp &vi1>;
/* Memory bandwidth in kB/s during tests */
nvidia,test-bw = <2400000>;
};
ivccontrol@3 {
compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control";
nvidia,service = "capture-control";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <64>;
nvidia,frame-size = <320>;
};
ivccapture@4 {
compatible = "nvidia,tegra186-camera-ivc-protocol-capture";
nvidia,service = "capture";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <512>;
nvidia,frame-size = <64>;
};
diag@5 {
compatible = "nvidia,tegra186-camera-diagnostics";
nvidia,service = "diag";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <64>;
};
};
rtcpu_trace: tegra-rtcpu-trace {
nvidia,enable-printk;
nvidia,interval-ms = <50>;
nvidia,log-prefix = "[RCE]";
};
capture_vi: tegra-capture-vi {
compatible = "nvidia,tegra-camrtc-capture-vi";
nvidia,vi-devices = <&vi0 &vi1>;
nvidia,vi-mapping-size = <6>;
nvidia,vi-mapping =
<0 0>,
<1 0>,
<2 1>,
<3 1>,
<4 0>,
<5 1>;
nvidia,vi-mapping-names = "csi-stream-id", "vi-unit-id";
nvidia,vi-max-channels = <72>;
};
reserved-memory {
rce_resv: rce-reservation {
iommu-addresses = <&tegra_rce 0x0 0x00000000 0x00000000 0xA0000000>,
<&tegra_rce 0x0 0xC0000000 0xffffffff 0x3fffffff>;
};
camdbg_reserved: camdbg_carveout {
compatible = "nvidia,camdbg_carveout";
size = <0 0x3200000>;
alignment = <0 0x100000>;
alloc-ranges = <0x1 0 0x1 0>;
status = "disabled";
};
};
};

377
nv-soc/tegra234-soc-display-overlay.dtsi
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@@ -4,201 +4,192 @@
#include <dt-bindings/power/tegra234-powergate.h>
/ {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-display@0 {
target-path = "/";
__overlay__ {
#endif
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
fb0_reserved: framebuffer@0,0 {
compatible = "framebuffer";
reg = <0x00 0x00 0x00 0x00>;
iommu-addresses = <&display 0x0 0x0 0x0 0x0>;
no-map;
status = "disabled";
};
};
dce@d800000 {
compatible = "nvidia,tegra234-dce";
reg = <0x0 0x0d800000 0x0 0x00800000>;
interrupts =
<0 376 0x4>,
<0 377 0x4>;
interrupt-names = "wdt-remote",
"dce-sm0";
iommus = <&smmu_niso0 TEGRA234_SID_DCE>;
status = "disabled";
};
display: display@13800000 {
compatible = "nvidia,tegra234-display";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
nvidia,num-dpaux-instance = <1>;
reg-names = "nvdisplay", "dpaux0", "hdacodec", "mipical";
reg = <0x0 0x13800000 0x0 0xEFFFF /* nvdisplay */
0x0 0x155C0000 0x0 0xFFFF /* dpaux0 */
0x0 0x0242c000 0x0 0x1000 /* hdacodec */
0x0 0x03990000 0x0 0x10000>; /* mipical */
interrupt-names = "nvdisplay", "dpaux0", "hdacodec";
interrupts = <0 416 4
0 419 4
0 61 4>;
nvidia,bpmp = <&bpmp>;
clocks = <&bpmp TEGRA234_CLK_HUB>,
<&bpmp TEGRA234_CLK_DISP>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P1>,
<&bpmp TEGRA234_CLK_DPAUX>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_DSIPLL_VCO>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTPN>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_VCO>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTB>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV10>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV25>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV27PN>,
<&bpmp TEGRA234_CLK_SPPLL1_VCO>,
<&bpmp TEGRA234_CLK_SPPLL1_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL1_DIV27PN>,
<&bpmp TEGRA234_CLK_VPLL0_REF>,
<&bpmp TEGRA234_CLK_VPLL0>,
<&bpmp TEGRA234_CLK_VPLL1>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0_REF>,
<&bpmp TEGRA234_CLK_RG0>,
<&bpmp TEGRA234_CLK_RG1>,
<&bpmp TEGRA234_CLK_DISPPLL>,
<&bpmp TEGRA234_CLK_DISPHUBPLL>,
<&bpmp TEGRA234_CLK_DSI_LP>,
<&bpmp TEGRA234_CLK_DSI_CORE>,
<&bpmp TEGRA234_CLK_DSI_PIXEL>,
<&bpmp TEGRA234_CLK_PRE_SOR0>,
<&bpmp TEGRA234_CLK_PRE_SOR1>,
<&bpmp TEGRA234_CLK_DP_LINK_REF>,
<&bpmp TEGRA234_CLK_SOR_LINKA_INPUT>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
<&bpmp TEGRA234_CLK_RG0_M>,
<&bpmp TEGRA234_CLK_RG1_M>,
<&bpmp TEGRA234_CLK_SOR0_M>,
<&bpmp TEGRA234_CLK_SOR1_M>,
<&bpmp TEGRA234_CLK_PLLHUB>,
<&bpmp TEGRA234_CLK_SOR0>,
<&bpmp TEGRA234_CLK_SOR1>,
<&bpmp TEGRA234_CLK_SOR_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SF0>,
<&bpmp TEGRA234_CLK_SF0>,
<&bpmp TEGRA234_CLK_SF1>,
<&bpmp TEGRA234_CLK_DSI_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SOR0_REF>,
<&bpmp TEGRA234_CLK_PRE_SOR1_REF>,
<&bpmp TEGRA234_CLK_SOR0_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR1_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR0_REF>,
<&bpmp TEGRA234_CLK_SOR1_REF>,
<&bpmp TEGRA234_CLK_OSC>,
<&bpmp TEGRA234_CLK_DSC>,
<&bpmp TEGRA234_CLK_MAUD>,
<&bpmp TEGRA234_CLK_AZA_2XBIT>,
<&bpmp TEGRA234_CLK_AZA_BIT>,
<&bpmp TEGRA234_CLK_MIPI_CAL>,
<&bpmp TEGRA234_CLK_UART_FST_MIPI_CAL>,
<&bpmp TEGRA234_CLK_SOR0_DIV>;
clock-names = "nvdisplayhub_clk",
"nvdisplay_disp_clk",
"nvdisplay_p0_clk",
"nvdisplay_p1_clk",
"dpaux0_clk",
"fuse_clk",
"dsipll_vco_clk",
"dsipll_clkoutpn_clk",
"dsipll_clkouta_clk",
"sppll0_vco_clk",
"sppll0_clkoutpn_clk",
"sppll0_clkouta_clk",
"sppll0_clkoutb_clk",
"sppll0_div10_clk",
"sppll0_div25_clk",
"sppll0_div27_clk",
"sppll1_vco_clk",
"sppll1_clkoutpn_clk",
"sppll1_div27_clk",
"vpll0_ref_clk",
"vpll0_clk",
"vpll1_clk",
"nvdisplay_p0_ref_clk",
"rg0_clk",
"rg1_clk",
"disppll_clk",
"disphubpll_clk",
"dsi_lp_clk",
"dsi_core_clk",
"dsi_pixel_clk",
"pre_sor0_clk",
"pre_sor1_clk",
"dp_link_ref_clk",
"sor_linka_input_clk",
"sor_linka_afifo_clk",
"sor_linka_afifo_m_clk",
"rg0_m_clk",
"rg1_m_clk",
"sor0_m_clk",
"sor1_m_clk",
"pllhub_clk",
"sor0_clk",
"sor1_clk",
"sor_pad_input_clk",
"pre_sf0_clk",
"sf0_clk",
"sf1_clk",
"dsi_pad_input_clk",
"pre_sor0_ref_clk",
"pre_sor1_ref_clk",
"sor0_ref_pll_clk",
"sor1_ref_pll_clk",
"sor0_ref_clk",
"sor1_ref_clk",
"osc_clk",
"dsc_clk",
"maud_clk",
"aza_2xbit_clk",
"aza_bit_clk",
"mipi_cal_clk",
"uart_fst_mipi_cal_clk",
"sor0_div_clk";
resets = <&bpmp TEGRA234_RESET_NVDISPLAY>,
<&bpmp TEGRA234_RESET_DPAUX>,
<&bpmp TEGRA234_RESET_DSI_CORE>,
<&bpmp TEGRA234_RESET_MIPI_CAL>;
reset-names = "nvdisplay_reset",
"dpaux0_reset",
"dsi_core_reset",
"mipi_cal_reset";
status = "disabled";
memory-region = <&fb0_reserved>;
nvidia,disp-sw-soc-chip-id = <0x2350>;
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
#endif
iommus = <&smmu_iso TEGRA234_SID_ISO_NVDISPLAY>;
non-coherent;
nvdisplay-niso {
compatible = "nvidia,tegra234-display-niso";
iommus = <&smmu_niso0 TEGRA234_SID_NVDISPLAY>;
dma-coherent;
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
fb0_reserved: framebuffer@0,0 {
compatible = "framebuffer";
reg = <0x00 0x00 0x00 0x00>;
iommu-addresses = <&display 0x0 0x0 0x0 0x0>;
no-map;
status = "disabled";
};
};
dce@d800000 {
compatible = "nvidia,tegra234-dce";
reg = <0x0 0x0d800000 0x0 0x00800000>;
interrupts =
<0 376 0x4>,
<0 377 0x4>;
interrupt-names = "wdt-remote",
"dce-sm0";
iommus = <&smmu_niso0 TEGRA234_SID_DCE>;
status = "disabled";
};
display: display@13800000 {
compatible = "nvidia,tegra234-display";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
nvidia,num-dpaux-instance = <1>;
reg-names = "nvdisplay", "dpaux0", "hdacodec", "mipical";
reg = <0x0 0x13800000 0x0 0xEFFFF /* nvdisplay */
0x0 0x155C0000 0x0 0xFFFF /* dpaux0 */
0x0 0x0242c000 0x0 0x1000 /* hdacodec */
0x0 0x03990000 0x0 0x10000>; /* mipical */
interrupt-names = "nvdisplay", "dpaux0", "hdacodec";
interrupts = <0 416 4
0 419 4
0 61 4>;
nvidia,bpmp = <&bpmp>;
clocks = <&bpmp TEGRA234_CLK_HUB>,
<&bpmp TEGRA234_CLK_DISP>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P1>,
<&bpmp TEGRA234_CLK_DPAUX>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_DSIPLL_VCO>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTPN>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_VCO>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTB>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV10>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV25>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV27PN>,
<&bpmp TEGRA234_CLK_SPPLL1_VCO>,
<&bpmp TEGRA234_CLK_SPPLL1_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL1_DIV27PN>,
<&bpmp TEGRA234_CLK_VPLL0_REF>,
<&bpmp TEGRA234_CLK_VPLL0>,
<&bpmp TEGRA234_CLK_VPLL1>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0_REF>,
<&bpmp TEGRA234_CLK_RG0>,
<&bpmp TEGRA234_CLK_RG1>,
<&bpmp TEGRA234_CLK_DISPPLL>,
<&bpmp TEGRA234_CLK_DISPHUBPLL>,
<&bpmp TEGRA234_CLK_DSI_LP>,
<&bpmp TEGRA234_CLK_DSI_CORE>,
<&bpmp TEGRA234_CLK_DSI_PIXEL>,
<&bpmp TEGRA234_CLK_PRE_SOR0>,
<&bpmp TEGRA234_CLK_PRE_SOR1>,
<&bpmp TEGRA234_CLK_DP_LINK_REF>,
<&bpmp TEGRA234_CLK_SOR_LINKA_INPUT>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
<&bpmp TEGRA234_CLK_RG0_M>,
<&bpmp TEGRA234_CLK_RG1_M>,
<&bpmp TEGRA234_CLK_SOR0_M>,
<&bpmp TEGRA234_CLK_SOR1_M>,
<&bpmp TEGRA234_CLK_PLLHUB>,
<&bpmp TEGRA234_CLK_SOR0>,
<&bpmp TEGRA234_CLK_SOR1>,
<&bpmp TEGRA234_CLK_SOR_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SF0>,
<&bpmp TEGRA234_CLK_SF0>,
<&bpmp TEGRA234_CLK_SF1>,
<&bpmp TEGRA234_CLK_DSI_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SOR0_REF>,
<&bpmp TEGRA234_CLK_PRE_SOR1_REF>,
<&bpmp TEGRA234_CLK_SOR0_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR1_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR0_REF>,
<&bpmp TEGRA234_CLK_SOR1_REF>,
<&bpmp TEGRA234_CLK_OSC>,
<&bpmp TEGRA234_CLK_DSC>,
<&bpmp TEGRA234_CLK_MAUD>,
<&bpmp TEGRA234_CLK_AZA_2XBIT>,
<&bpmp TEGRA234_CLK_AZA_BIT>,
<&bpmp TEGRA234_CLK_MIPI_CAL>,
<&bpmp TEGRA234_CLK_UART_FST_MIPI_CAL>,
<&bpmp TEGRA234_CLK_SOR0_DIV>;
clock-names = "nvdisplayhub_clk",
"nvdisplay_disp_clk",
"nvdisplay_p0_clk",
"nvdisplay_p1_clk",
"dpaux0_clk",
"fuse_clk",
"dsipll_vco_clk",
"dsipll_clkoutpn_clk",
"dsipll_clkouta_clk",
"sppll0_vco_clk",
"sppll0_clkoutpn_clk",
"sppll0_clkouta_clk",
"sppll0_clkoutb_clk",
"sppll0_div10_clk",
"sppll0_div25_clk",
"sppll0_div27_clk",
"sppll1_vco_clk",
"sppll1_clkoutpn_clk",
"sppll1_div27_clk",
"vpll0_ref_clk",
"vpll0_clk",
"vpll1_clk",
"nvdisplay_p0_ref_clk",
"rg0_clk",
"rg1_clk",
"disppll_clk",
"disphubpll_clk",
"dsi_lp_clk",
"dsi_core_clk",
"dsi_pixel_clk",
"pre_sor0_clk",
"pre_sor1_clk",
"dp_link_ref_clk",
"sor_linka_input_clk",
"sor_linka_afifo_clk",
"sor_linka_afifo_m_clk",
"rg0_m_clk",
"rg1_m_clk",
"sor0_m_clk",
"sor1_m_clk",
"pllhub_clk",
"sor0_clk",
"sor1_clk",
"sor_pad_input_clk",
"pre_sf0_clk",
"sf0_clk",
"sf1_clk",
"dsi_pad_input_clk",
"pre_sor0_ref_clk",
"pre_sor1_ref_clk",
"sor0_ref_pll_clk",
"sor1_ref_pll_clk",
"sor0_ref_clk",
"sor1_ref_clk",
"osc_clk",
"dsc_clk",
"maud_clk",
"aza_2xbit_clk",
"aza_bit_clk",
"mipi_cal_clk",
"uart_fst_mipi_cal_clk",
"sor0_div_clk";
resets = <&bpmp TEGRA234_RESET_NVDISPLAY>,
<&bpmp TEGRA234_RESET_DPAUX>,
<&bpmp TEGRA234_RESET_DSI_CORE>,
<&bpmp TEGRA234_RESET_MIPI_CAL>;
reset-names = "nvdisplay_reset",
"dpaux0_reset",
"dsi_core_reset",
"mipi_cal_reset";
status = "disabled";
memory-region = <&fb0_reserved>;
nvidia,disp-sw-soc-chip-id = <0x2350>;
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
#endif
iommus = <&smmu_iso TEGRA234_SID_ISO_NVDISPLAY>;
non-coherent;
nvdisplay-niso {
compatible = "nvidia,tegra234-display-niso";
iommus = <&smmu_niso0 TEGRA234_SID_NVDISPLAY>;
dma-coherent;
};
};
};

2039
nv-soc/tegra234-soc-overlay.dtsi
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File diff suppressed because it is too large Load Diff

1091
nv-soc/tegra234-soc-prod-overlay.dtsi
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File diff suppressed because it is too large Load Diff

199
nv-soc/tegra234-soc-safetyservice-fsicom.dtsi
View File

@@ -5,110 +5,101 @@
#include <dt-bindings/memory/tegra234-mc.h>
/ {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-fsicom@0 {
target-path = "/";
__overlay__ {
#endif
reserved-memory {
fsicom_resv: reservation-fsicom {
iommu-addresses = <&fsiccplex_com 0x0 0x0 0x0 0xf0000000>,
<&fsiccplex_com 0x0 0xf1000000 0xffffffff 0x0effffff>;
};
};
fsiccplex_com:fsicom_client {
compatible = "nvidia,tegra234-fsicom-client";
mboxes =
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(2)>,
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>;
mbox-names = "fsi-tx", "fsi-rx";
iommus = <&smmu_niso1 TEGRA234_SID_FSI>;
memory-region = <&fsicom_resv>;
dma-coherent;
status = "disabled";
};
safetyservices_epl_client {
compatible = "nvidia,tegra234-epl-client";
mboxes = <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(0)>;
mbox-names = "epl-tx";
reg = <0x0 0x00110000 0x0 0x4>,
<0x0 0x00110004 0x0 0x4>,
<0x0 0x00120000 0x0 0x4>,
<0x0 0x00120004 0x0 0x4>,
<0x0 0x00130000 0x0 0x4>,
<0x0 0x00130004 0x0 0x4>,
<0x0 0x00140000 0x0 0x4>,
<0x0 0x00140004 0x0 0x4>,
<0x0 0x00150000 0x0 0x4>,
<0x0 0x00150004 0x0 0x4>,
<0x0 0x024e0038 0x0 0x4>;
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR0_SW_ERR_CODE_0 */
client-misc-sw-generic-err0 = "fsicom_client";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR1_SW_ERR_CODE_0 */
client-misc-sw-generic-err1 = "gk20b";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR3_SW_ERR_CODE_0 */
client-misc-sw-generic-err3 = "gk20d";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR4_SW_ERR_CODE_0 */
client-misc-sw-generic-err4 = "gk20e";
status = "disabled";
};
FsiComIvc {
compatible = "nvidia,tegra-fsicom-channels";
status = "disabled";
nChannel = <7>;
channel_0 {
frame-count = <4>;
frame-size = <1024>;
NvSciCh = "nvfsicom_EPD";
};
channel_1 {
frame-count = <30>;
frame-size = <64>;
NvSciCh = "nvfsicom_CcplexApp";
};
channel_2 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_CcplexApp_state_change";
};
channel_3 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_app1";
};
channel_4 {
frame-count = <2>;
frame-size = <512>;
NvSciCh = "nvfsicom_app2";
};
channel_5 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_appGR";
};
channel_6 {
frame-count = <4>;
frame-size = <10240>;
};
};
FsiComClientChConfigEpd {
compatible = "nvidia,tegra-fsicom-EPD";
status = "disabled";
channelid_list = <0>;
};
#ifndef REMOVE_FRAGMENT_SYNTAX
reserved-memory {
fsicom_resv: reservation-fsicom {
iommu-addresses = <&fsiccplex_com 0x0 0x0 0x0 0xf0000000>,
<&fsiccplex_com 0x0 0xf1000000 0xffffffff 0x0effffff>;
};
};
#endif
fsiccplex_com:fsicom_client {
compatible = "nvidia,tegra234-fsicom-client";
mboxes =
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(2)>,
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>;
mbox-names = "fsi-tx", "fsi-rx";
iommus = <&smmu_niso1 TEGRA234_SID_FSI>;
memory-region = <&fsicom_resv>;
dma-coherent;
status = "disabled";
};
safetyservices_epl_client {
compatible = "nvidia,tegra234-epl-client";
mboxes = <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(0)>;
mbox-names = "epl-tx";
reg = <0x0 0x00110000 0x0 0x4>,
<0x0 0x00110004 0x0 0x4>,
<0x0 0x00120000 0x0 0x4>,
<0x0 0x00120004 0x0 0x4>,
<0x0 0x00130000 0x0 0x4>,
<0x0 0x00130004 0x0 0x4>,
<0x0 0x00140000 0x0 0x4>,
<0x0 0x00140004 0x0 0x4>,
<0x0 0x00150000 0x0 0x4>,
<0x0 0x00150004 0x0 0x4>,
<0x0 0x024e0038 0x0 0x4>;
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR0_SW_ERR_CODE_0 */
client-misc-sw-generic-err0 = "fsicom_client";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR1_SW_ERR_CODE_0 */
client-misc-sw-generic-err1 = "gk20b";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR3_SW_ERR_CODE_0 */
client-misc-sw-generic-err3 = "gk20d";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR4_SW_ERR_CODE_0 */
client-misc-sw-generic-err4 = "gk20e";
status = "disabled";
};
FsiComIvc {
compatible = "nvidia,tegra-fsicom-channels";
status = "disabled";
nChannel = <7>;
channel_0 {
frame-count = <4>;
frame-size = <1024>;
NvSciCh = "nvfsicom_EPD";
};
channel_1 {
frame-count = <30>;
frame-size = <64>;
NvSciCh = "nvfsicom_CcplexApp";
};
channel_2 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_CcplexApp_state_change";
};
channel_3 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_app1";
};
channel_4 {
frame-count = <2>;
frame-size = <512>;
NvSciCh = "nvfsicom_app2";
};
channel_5 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_appGR";
};
channel_6 {
frame-count = <4>;
frame-size = <10240>;
};
};
FsiComClientChConfigEpd {
compatible = "nvidia,tegra-fsicom-EPD";
status = "disabled";
channelid_list = <0>;
};
};

183
nv-soc/tegra234-soc-thermal-shutdown.dtsi
View File

@@ -4,104 +4,95 @@
#define TEGRA234_THERMAL_SHUTDOWN_TEMP 104500
/ {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal-shutdown@0 {
target-path = "/";
__overlay__ {
#endif
thermal-zones {
cpu-thermal {
trips {
cpu_sw_shutdown: cpu-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
gpu-thermal {
trips {
gpu_sw_shutdown: gpu-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
cv0-thermal {
trips {
cv0_sw_shutdown: cv0-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
cv1-thermal {
trips {
cv1_sw_shutdown: cv1-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
cv2-thermal {
trips {
cv2_sw_shutdown: cv2-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
soc0-thermal {
trips {
soc0_sw_shutdown: soc0-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
soc1-thermal {
trips {
soc1_sw_shutdown: soc1-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
soc2-thermal {
trips {
soc2_sw_shutdown: soc2-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
tj-thermal {
trips {
tj_sw_shutdown: tj-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
thermal-zones {
cpu-thermal {
trips {
cpu_sw_shutdown: cpu-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
gpu-thermal {
trips {
gpu_sw_shutdown: gpu-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
cv0-thermal {
trips {
cv0_sw_shutdown: cv0-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
cv1-thermal {
trips {
cv1_sw_shutdown: cv1-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
cv2-thermal {
trips {
cv2_sw_shutdown: cv2-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
soc0-thermal {
trips {
soc0_sw_shutdown: soc0-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
soc1-thermal {
trips {
soc1_sw_shutdown: soc1-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
soc2-thermal {
trips {
soc2_sw_shutdown: soc2-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
};
tj-thermal {
trips {
tj_sw_shutdown: tj-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
};

431
nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi
View File

@@ -6,226 +6,217 @@
#define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
/ {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal-slowdown-cluster@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 {
gpu@17000000 {
#cooling-cells = <2>;
};
};
cpus{
cpu@0 {
#cooling-cells = <2>;
};
cpu@10000 {
#cooling-cells = <2>;
};
cpu@20000 {
#cooling-cells = <2>;
};
};
thermal-zones {
cpu-thermal {
trips {
cpu_sw_slowdown: cpu-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cpu_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu-thermal {
trips {
gpu_sw_slowdown: gpu-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&gpu_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&gpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv0-thermal {
trips {
cv0_sw_slowdown: cv0-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv0_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv1-thermal {
trips {
cv1_sw_slowdown: cv1-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv1_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv2-thermal {
trips {
cv2_sw_slowdown: cv2-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv2_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc0-thermal {
trips {
soc0_sw_slowdown: soc0-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc0_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc1-thermal {
trips {
soc1_sw_slowdown: soc1-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc1_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc2-thermal {
trips {
soc2_sw_slowdown: soc2-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc2_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
bus@0 {
gpu@17000000 {
#cooling-cells = <2>;
};
};
cpus{
cpu@0 {
#cooling-cells = <2>;
};
cpu@10000 {
#cooling-cells = <2>;
};
cpu@20000 {
#cooling-cells = <2>;
};
};
thermal-zones {
cpu-thermal {
trips {
cpu_sw_slowdown: cpu-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cpu_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu-thermal {
trips {
gpu_sw_slowdown: gpu-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&gpu_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&gpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv0-thermal {
trips {
cv0_sw_slowdown: cv0-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv0_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv1-thermal {
trips {
cv1_sw_slowdown: cv1-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv1_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv2-thermal {
trips {
cv2_sw_slowdown: cv2-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv2_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc0-thermal {
trips {
soc0_sw_slowdown: soc0-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc0_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc1-thermal {
trips {
soc1_sw_slowdown: soc1-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc1_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc2-thermal {
trips {
soc2_sw_slowdown: soc2-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc2_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
#endif
};

503
nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi
View File

@@ -6,262 +6,253 @@
#define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
/ {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal-slowdown-corepair@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 {
gpu@17000000 {
#cooling-cells = <2>;
};
};
cpus{
cpu@0 {
#cooling-cells = <2>;
};
cpu@200 {
#cooling-cells = <2>;
};
cpu@10000 {
#cooling-cells = <2>;
};
cpu@10200 {
#cooling-cells = <2>;
};
cpu@20000 {
#cooling-cells = <2>;
};
cpu@20200 {
#cooling-cells = <2>;
};
};
thermal-zones {
cpu-thermal {
trips {
cpu_sw_slowdown: cpu-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cpu_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu-thermal {
trips {
gpu_sw_slowdown: gpu-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&gpu_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&gpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv0-thermal {
trips {
cv0_sw_slowdown: cv0-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv0_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv1-thermal {
trips {
cv1_sw_slowdown: cv1-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv1_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv2-thermal {
trips {
cv2_sw_slowdown: cv2-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv2_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc0-thermal {
trips {
soc0_sw_slowdown: soc0-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc0_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc1-thermal {
trips {
soc1_sw_slowdown: soc1-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc1_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc2-thermal {
trips {
soc2_sw_slowdown: soc2-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc2_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
bus@0 {
gpu@17000000 {
#cooling-cells = <2>;
};
};
cpus{
cpu@0 {
#cooling-cells = <2>;
};
cpu@200 {
#cooling-cells = <2>;
};
cpu@10000 {
#cooling-cells = <2>;
};
cpu@10200 {
#cooling-cells = <2>;
};
cpu@20000 {
#cooling-cells = <2>;
};
cpu@20200 {
#cooling-cells = <2>;
};
};
thermal-zones {
cpu-thermal {
trips {
cpu_sw_slowdown: cpu-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cpu_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
gpu-thermal {
trips {
gpu_sw_slowdown: gpu-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&gpu_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&gpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv0-thermal {
trips {
cv0_sw_slowdown: cv0-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv0_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv1-thermal {
trips {
cv1_sw_slowdown: cv1-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv1_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cv2-thermal {
trips {
cv2_sw_slowdown: cv2-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&cv2_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&cv2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc0-thermal {
trips {
soc0_sw_slowdown: soc0-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc0_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc1-thermal {
trips {
soc1_sw_slowdown: soc1-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc1_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
soc2-thermal {
trips {
soc2_sw_slowdown: soc2-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
type = "passive";
};
};
cooling-maps {
map-cpufreq {
trip = <&soc2_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map-devfreq {
trip = <&soc2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
#endif
};

81
nv-soc/tegra234-soc-thermal.dtsi
View File

@@ -4,59 +4,50 @@
#define TEGRA234_THERMAL_POLLING_DELAY 1000
/ {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal@0 {
target-path = "/";
__overlay__ {
#endif
thermal-zones {
cpu-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
thermal-zones {
cpu-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
gpu-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
gpu-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
cv0-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
cv0-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
cv1-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
cv1-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
cv2-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
cv2-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
soc0-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
soc0-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
soc1-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
soc1-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
soc2-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
soc2-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
tj-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
tj-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
};
#endif
};