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nv-public: remove REMOVE_FRAGMENT_SYNTAX

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These preprocessor conditionals were a temporary step to facilitate
step by step reviews.  Remove them and fix indentation.

Bug 4290389

Change-Id: Iecdbdf1869bec00538530d59420622d8563a116a
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3000004
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Gautham Srinivasan <gauthams@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Brad Griffis
2023-10-19 00:50:10 +00:00
committed by mobile promotions
parent ff77a8a1cd
commit 8f0cbdad83
35 changed files with 8784 additions and 9020 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
nv-platform/tegra234-camera-p3785.dtsi
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@@ -6,11 +6,6 @@
#define CAM0_PWDN TEGRA234_AON_GPIO(AA, 4) #define CAM0_PWDN TEGRA234_AON_GPIO(AA, 4)
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-camera@0 {
target-path = "/";
__overlay__ {
#endif
gpio@c2f0000 { gpio@c2f0000 {
camera-control-output-high { camera-control-output-high {
gpio-hog; gpio-hog;
@@ -402,8 +397,4 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-platform/tegra234-dcb-p3737-0000-p3701-0000.dtsi
View File

@@ -2,11 +2,6 @@
// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-dcb@0 {
target-path = "/";
__overlay__ {
#endif
display@13800000 { display@13800000 {
nvidia,dcb-image = [ nvidia,dcb-image = [
55 aa 16 00 00 37 34 30 30 e9 4c 19 77 cc 56 49 55 aa 16 00 00 37 34 30 30 e9 4c 19 77 cc 56 49
@@ -536,8 +531,4 @@
40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00 40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 ]; 00 00 00 00 00 00 00 ];
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-platform/tegra234-p3701-0000-prod-overlay.dtsi
View File

@@ -2,11 +2,6 @@
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-p3701-prod@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 { bus@0 {
aon@c000000 { aon@c000000 {
prod-settings { prod-settings {
@@ -250,8 +245,4 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-platform/tegra234-p3701-0000.dtsi
View File

@@ -4,11 +4,6 @@
#include "tegra234-p3701-0000-prod-overlay.dtsi" #include "tegra234-p3701-0000-prod-overlay.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3701-0000@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 { bus@0 {
i2c@c240000 { i2c@c240000 {
ina3221@40 { ina3221@40 {
@@ -147,8 +142,4 @@
status = "okay"; status = "okay";
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-platform/tegra234-p3701-0008.dtsi
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@@ -2,11 +2,6 @@
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3701-0008@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 { bus@0 {
i2c@c240000 { i2c@c240000 {
ina3221@40 { ina3221@40 {
@@ -284,8 +279,4 @@
status = "okay"; status = "okay";
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

1
nv-platform/tegra234-p3737-0000+p3701-0000-nv.dts
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@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "tegra234-p3737-0000+p3701-0000.dts" #include "tegra234-p3737-0000+p3701-0000.dts"
#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi" #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3737-0000+p3701-0004-nv.dts
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@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3737-0000+p3701-0004.dts" #include "staging/tegra234-p3737-0000+p3701-0004.dts"
#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi" #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3737-0000+p3701-0005-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3737-0000+p3701-0005.dts" #include "staging/tegra234-p3737-0000+p3701-0005.dts"
#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi" #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3737-0000+p3701-0008-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3737-0000+p3701-0008.dts" #include "staging/tegra234-p3737-0000+p3701-0008.dts"
#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi" #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"

10
nv-platform/tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi
View File

@@ -12,12 +12,6 @@
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi" #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
compatible = "nvidia,p3737-0000+p3701-0000";
fragment-t234-p3737-p3701@0 {
target-path = "/";
__overlay__ {
#endif
cpus { cpus {
idle-states { idle-states {
c7 { c7 {
@@ -333,8 +327,4 @@
display@13800000 { display@13800000 {
status = "okay"; status = "okay";
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-platform/tegra234-p3737-0000.dtsi
View File

@@ -2,11 +2,6 @@
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3737-0000@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 { bus@0 {
spi@3210000{ /* SPI1 in 40 pin conn */ spi@3210000{ /* SPI1 in 40 pin conn */
spi@0 { /* chip select 0 */ spi@0 { /* chip select 0 */
@@ -127,8 +122,4 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

11
nv-platform/tegra234-p3740-0002+p3701-0008-nv-common.dtsi
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@@ -12,13 +12,6 @@
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi" #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
compatible = "nvidia,p3740-0002+p3701-0008";
fragment-t234-p3740-p3701@0 {
target-path = "/";
__overlay__ {
#endif
chosen { chosen {
bootargs = "console=ttyTCU0,115200n8"; bootargs = "console=ttyTCU0,115200n8";
}; };
@@ -291,8 +284,4 @@
display@13800000 { display@13800000 {
status = "okay"; status = "okay";
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

1
nv-platform/tegra234-p3740-0002+p3701-0008-nv-safety.dts
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@@ -3,7 +3,6 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "tegra234-p3740-0002+p3701-0008.dts" #include "tegra234-p3740-0002+p3701-0008.dts"
#include "tegra234-p3740-0002+p3701-0008-nv-common.dtsi" #include "tegra234-p3740-0002+p3701-0008-nv-common.dtsi"
#include "tegra234-p3740-0002+p3701-0008-safety.dtsi" #include "tegra234-p3740-0002+p3701-0008-safety.dtsi"

1
nv-platform/tegra234-p3740-0002+p3701-0008-nv.dts
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@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "tegra234-p3740-0002+p3701-0008.dts" #include "tegra234-p3740-0002+p3701-0008.dts"
#include "tegra234-p3740-0002+p3701-0008-nv-common.dtsi" #include "tegra234-p3740-0002+p3701-0008-nv-common.dtsi"

9
nv-platform/tegra234-p3740-0002+p3701-0008-safety.dtsi
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@@ -4,11 +4,6 @@
#include "nv-soc/tegra234-soc-safetyservice-fsicom.dtsi" #include "nv-soc/tegra234-soc-safetyservice-fsicom.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3740-p3701-safety@0 {
target-path = "/";
__overlay__ {
#endif
compatible = "nvidia,p3740-0002+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234"; compatible = "nvidia,p3740-0002+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234";
bus@0 { bus@0 {
@@ -222,8 +217,4 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-platform/tegra234-p3740-0002.dtsi
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@@ -4,11 +4,6 @@
#include "nv-soc/tegra234-soc-audio-dai-links.dtsi" #include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3740-0002@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 { bus@0 {
i2c@31c0000 { i2c@31c0000 {
typec: stusb1600@28 { typec: stusb1600@28 {
@@ -233,8 +228,4 @@
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

10
nv-platform/tegra234-p3767-0000.dtsi
View File

@@ -6,12 +6,6 @@
#include <dt-bindings/interrupt/tegra234-irq.h> #include <dt-bindings/interrupt/tegra234-irq.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
p3767-0000-fragment@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 { bus@0 {
mmc@3400000 { mmc@3400000 {
no-sdio; no-sdio;
@@ -76,8 +70,4 @@
status = "okay"; status = "okay";
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

1
nv-platform/tegra234-p3768-0000+p3767-0000-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "tegra234-p3768-0000+p3767-0000.dts" #include "tegra234-p3768-0000+p3767-0000.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi" #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3768-0000+p3767-0001-nv.dts
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@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3768-0000+p3767-0001.dts" #include "staging/tegra234-p3768-0000+p3767-0001.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi" #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3768-0000+p3767-0003-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3768-0000+p3767-0003.dts" #include "staging/tegra234-p3768-0000+p3767-0003.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi" #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3768-0000+p3767-0004-nv.dts
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@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3768-0000+p3767-0004.dts" #include "staging/tegra234-p3768-0000+p3767-0004.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi" #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3768-0000+p3767-0005-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "tegra234-p3768-0000+p3767-0005.dts" #include "tegra234-p3768-0000+p3767-0005.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi" #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

11
nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi
View File

@@ -12,13 +12,6 @@
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi" #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
overlay-name = "Tegra234 P3768-0000+P3767-0000 Overlay";
fragment-t234-p3768-p3767@0 {
target-path = "/";
__overlay__ {
#endif
bpmp { bpmp {
i2c { i2c {
vrs@3c { vrs@3c {
@@ -455,8 +448,4 @@
tegra-hsp@b950000 { tegra-hsp@b950000 {
status = "okay"; status = "okay";
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-platform/tegra234-p3768-0000.dtsi
View File

@@ -2,11 +2,6 @@
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3768-0000@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 { bus@0 {
aconnect@2900000 { aconnect@2900000 {
@@ -38,8 +33,4 @@
hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { }; hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

16
nv-soc/tegra234-base-overlay.dtsi
View File

@@ -21,14 +21,6 @@
#define TEGRA234_POWER_DOMAIN_DLAB 33U #define TEGRA234_POWER_DOMAIN_DLAB 33U
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
overlay-name = "Add nvidia,t234 Overlay Support";
compatible = "nvidia,tegra234";
fragment-t234-base@0 {
target-path = "/";
__overlay__ {
#endif
aliases { aliases {
serial0 = "/bus@0/serial@3100000"; serial0 = "/bus@0/serial@3100000";
serial1 = "/bus@0/serial@3110000"; serial1 = "/bus@0/serial@3110000";
@@ -308,11 +300,11 @@
"eqos_rx_m", "eqos_rx_input", "eqos_rx_m", "eqos_rx_input",
"eqos_macsec_tx", "eqos_tx_divider", "eqos_macsec_tx", "eqos_tx_divider",
"eqos_macsec_rx"; "eqos_macsec_rx";
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2 #if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>, interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>,
<&mc TEGRA234_MEMORY_CLIENT_EQOSW>; <&mc TEGRA234_MEMORY_CLIENT_EQOSW>;
interconnect-names = "dma-mem", "write"; interconnect-names = "dma-mem", "write";
#endif #endif
iommus = <&smmu_niso1 TEGRA234_SID_EQOS>; iommus = <&smmu_niso1 TEGRA234_SID_EQOS>;
nvidia,num-dma-chans = <8>; nvidia,num-dma-chans = <8>;
nvidia,num-mtl-queues = <8>; nvidia,num-mtl-queues = <8>;
@@ -801,8 +793,4 @@
nvidia,vm-irq-id = <3>; nvidia,vm-irq-id = <3>;
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-soc/tegra234-soc-audio-dai-links.dtsi
View File

@@ -7,11 +7,6 @@
#define ADMAIF_CIF(i) (TEGRA186_ADMAIF_CIF_OFFSET + i - 1) #define ADMAIF_CIF(i) (TEGRA186_ADMAIF_CIF_OFFSET + i - 1)
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-audio-links@0 {
target-path = "/";
__overlay__ {
#endif
sound { sound {
/* ADMAIF <--> XBAR PCM links */ /* ADMAIF <--> XBAR PCM links */
admaif1_pcm_link: nvidia-audio-card,dai-link@0 { admaif1_pcm_link: nvidia-audio-card,dai-link@0 {
@@ -2278,8 +2273,4 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-soc/tegra234-soc-camera.dtsi
View File

@@ -12,11 +12,6 @@
#include <dt-bindings/memory/tegra234-mc.h> #include <dt-bindings/memory/tegra234-mc.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-camera@0 {
target-path = "/";
__overlay__ {
#endif
aliases { /* RCE is the Camera RTCPU */ aliases { /* RCE is the Camera RTCPU */
tegra-camera-rtcpu = "/rtcpu@bc00000"; tegra-camera-rtcpu = "/rtcpu@bc00000";
}; };
@@ -266,8 +261,4 @@
status = "disabled"; status = "disabled";
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-soc/tegra234-soc-display-overlay.dtsi
View File

@@ -4,11 +4,6 @@
#include <dt-bindings/power/tegra234-powergate.h> #include <dt-bindings/power/tegra234-powergate.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-display@0 {
target-path = "/";
__overlay__ {
#endif
reserved-memory { reserved-memory {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
@@ -197,8 +192,4 @@
dma-coherent; dma-coherent;
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-soc/tegra234-soc-overlay.dtsi
View File

@@ -16,11 +16,6 @@
#include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-soc@0 {
target-path = "/";
__overlay__ {
#endif
aliases { aliases {
nvdla0 = "/bus@0/host1x@13e00000/nvdla0@15880000"; nvdla0 = "/bus@0/host1x@13e00000/nvdla0@15880000";
nvdla1 = "/bus@0/host1x@13e00000/nvdla1@158c0000"; nvdla1 = "/bus@0/host1x@13e00000/nvdla1@158c0000";
@@ -1038,8 +1033,4 @@
status = "disabled"; status = "disabled";
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-soc/tegra234-soc-prod-overlay.dtsi
View File

@@ -2,11 +2,6 @@
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-soc-prod@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 { bus@0 {
i2c@3160000 { i2c@3160000 {
prod-settings { prod-settings {
@@ -556,8 +551,4 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-soc/tegra234-soc-safetyservice-fsicom.dtsi
View File

@@ -5,11 +5,6 @@
#include <dt-bindings/memory/tegra234-mc.h> #include <dt-bindings/memory/tegra234-mc.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-fsicom@0 {
target-path = "/";
__overlay__ {
#endif
reserved-memory { reserved-memory {
fsicom_resv: reservation-fsicom { fsicom_resv: reservation-fsicom {
iommu-addresses = <&fsiccplex_com 0x0 0x0 0x0 0xf0000000>, iommu-addresses = <&fsiccplex_com 0x0 0x0 0x0 0xf0000000>,
@@ -107,8 +102,4 @@
status = "disabled"; status = "disabled";
channelid_list = <0>; channelid_list = <0>;
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-soc/tegra234-soc-thermal-shutdown.dtsi
View File

@@ -4,11 +4,6 @@
#define TEGRA234_THERMAL_SHUTDOWN_TEMP 104500 #define TEGRA234_THERMAL_SHUTDOWN_TEMP 104500
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal-shutdown@0 {
target-path = "/";
__overlay__ {
#endif
thermal-zones { thermal-zones {
cpu-thermal { cpu-thermal {
trips { trips {
@@ -100,8 +95,4 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi
View File

@@ -6,11 +6,6 @@
#define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000 #define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal-slowdown-cluster@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 { bus@0 {
gpu@17000000 { gpu@17000000 {
#cooling-cells = <2>; #cooling-cells = <2>;
@@ -224,8 +219,4 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi
View File

@@ -6,11 +6,6 @@
#define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000 #define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal-slowdown-corepair@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 { bus@0 {
gpu@17000000 { gpu@17000000 {
#cooling-cells = <2>; #cooling-cells = <2>;
@@ -260,8 +255,4 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };

9
nv-soc/tegra234-soc-thermal.dtsi
View File

@@ -4,11 +4,6 @@
#define TEGRA234_THERMAL_POLLING_DELAY 1000 #define TEGRA234_THERMAL_POLLING_DELAY 1000
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal@0 {
target-path = "/";
__overlay__ {
#endif
thermal-zones { thermal-zones {
cpu-thermal { cpu-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
@@ -55,8 +50,4 @@
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
};
};
#endif
}; };