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nv-public: remove REMOVE_FRAGMENT_SYNTAX

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These preprocessor conditionals were a temporary step to facilitate
step by step reviews.  Remove them and fix indentation.

Bug 4290389

Change-Id: Iecdbdf1869bec00538530d59420622d8563a116a
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3000004
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Gautham Srinivasan <gauthams@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Brad Griffis
2023-10-19 00:50:10 +00:00
committed by mobile promotions
parent ff77a8a1cd
commit 8f0cbdad83
35 changed files with 8784 additions and 9020 deletions
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759
nv-platform/tegra234-camera-p3785.dtsi
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@@ -6,404 +6,395 @@
#define CAM0_PWDN TEGRA234_AON_GPIO(AA, 4) #define CAM0_PWDN TEGRA234_AON_GPIO(AA, 4)
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX gpio@c2f0000 {
fragment-camera@0 { camera-control-output-high {
target-path = "/"; gpio-hog;
__overlay__ { output-high;
#endif gpios = <CAM0_PWDN 0>;
gpio@c2f0000 { label = "cam0-pwdn";
camera-control-output-high { };
gpio-hog; };
output-high;
gpios = <CAM0_PWDN 0>; tegra-capture-vi {
label = "cam0-pwdn"; nvidia,vi-mapping =
<0 0>,
<1 0>,
<2 0>,
<3 0>,
<4 1>,
<5 1>;
num-channels = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
p3785_vi_in0: endpoint {
port-index = <0>;
bus-width = <8>;
remote-endpoint = <&p3785_csi_out0>;
}; };
}; };
};
tegra-capture-vi { };
nvidia,vi-mapping = bus@0 {
<0 0>, host1x@13e00000 {
<1 0>, nvcsi@15a00000 {
<2 0>,
<3 0>,
<4 1>,
<5 1>;
num-channels = <1>; num-channels = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
p3785_csi_in0: endpoint@0 {
port-index = <0>;
bus-width = <8>;
remote-endpoint = <&p3785_out0>;
};
};
port@1 {
reg = <1>;
p3785_csi_out0: endpoint@1 {
remote-endpoint = <&p3785_vi_in0>;
};
};
};
};
};
};
i2c@3180000 {
p3785@56 {
compatible = "nvidia,lt6911uxc";
/* I2C device address */
reg = <0x56>;
/* V4L2 device node location */
devnode = "video0";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
sensor_model = "p3785";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources
avdd-reg = "vana";
iovdd-reg = "vif";
dvdd-reg = "vdig";*/
/* Defines number of frames to be dropped by driver internally after applying */
/* sensor crop settings. Some sensors send corrupt frames after applying */
/* crop co-ordinates */
/*post_crop_frame_drop = "0";*/
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
reset-gpios = <&gpio_aon CAM0_PWDN GPIO_ACTIVE_HIGH>;
/**
* ==== Modes ====
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* == Signal properties ==
*
* phy_mode = "";
* PHY mode used by the MIPI lanes for this device
*
* tegra_sinterface = "";
* CSI Serial interface connected to tegra
* Incase of virtual HW devices, use virtual
* For SW emulated devices, use host
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* == Image format Properties ==
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* line_length = "";
* Pixel line length (width) for sensor mode.
*
* == Source Control Settings ==
*
* Gain factor used to convert fixed point integer to float
* Gain range [min_gain/gain_factor, max_gain/gain_factor]
* Gain step [step_gain/gain_factor is the smallest step that can be configured]
* Default gain [Default gain to be initialized for the control.
* use min_gain_val as default for optimal results]
* Framerate factor used to convert fixed point integer to float
* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
* Default Framerate [Default framerate to be initialized for the control.
* use max_framerate to get required performance]
* Exposure factor used to convert fixed point integer to float
* For convenience use 1 sec = 1000000us as conversion factor
* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
* Default Exposure Time [Default exposure to be initialized for the control.
* Set default exposure based on the default_framerate for optimal exposure settings]
* For convenience use 1 sec = 1000000us as conversion factor
*
* gain_factor = ""; (integer factor used for floating to fixed point conversion)
* min_gain_val = ""; (ceil to integer)
* max_gain_val = ""; (ceil to integer)
* step_gain_val = ""; (ceil to integer)
* default_gain = ""; (ceil to integer)
* Gain limits for mode
*
* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* step_exp_time = ""; (ceil to integer)
* default_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (sec)
*
* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
* min_framerate = ""; (ceil to integer)
* max_framerate = ""; (ceil to integer)
* step_framerate = ""; (ceil to integer)
* default_framerate = ""; (ceil to integer)
* Framerate limits for mode (fps)
*
* embedded_metadata_height = "";
* Sensor embedded metadata height in units of rows.
* If sensor does not support embedded metadata value should be 0.
* num_of_exposure = "";
* Digital overlap(Dol) frames
*
* num_of_ignored_lines = "";
* Used for cropping, eg. OB lines + Ignored area of effective pixel lines
*
* num_of_lines_offset_0 = "";
* Used for cropping, vertical blanking in front of short exposure data
* If more Dol frames are used, it can be extended, eg. num_of_lines_offset_1
*
* num_of_ignored_pixels = "";
* Used for cropping, The length of line info(pixels)
*
* num_of_left_margin_pixels = "";
* Used for cropping, the size of the left edge margin before
* the active pixel area (after ignored pixels)
*
* num_of_right_margin_pixels = "";
* Used for cropping, the size of the right edge margin after
* the active pixel area
*
*/
mode0 { // E2832_1920x1080_60Fps
mclk_khz = "24000";
num_lanes = "4";
tegra_sinterface = "serial_a";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1920";
active_h = "1080";
mode_type = "rgb";
pixel_phase = "rgb888";
csi_pixel_bit_depth = "24";
readout_orientation = "0";
line_length = "1920";
inherent_gain = "1";
mclk_multiplier = "24";
pix_clk_hz = "250000000";
gain_factor = "16";
framerate_factor = "1000000";
exposure_factor = "1000000";
min_gain_val = "16"; /* 1.00x */
max_gain_val = "170"; /* 10.66x */
step_gain_val = "1";
default_gain = "16"; /* 1.00x */
min_hdr_ratio = "1";
max_hdr_ratio = "1";
min_framerate = "2000000"; /* 2.0 fps */
max_framerate = "60000000"; /* 60.0 fps */
step_framerate = "1";
default_framerate = "60000000"; /* 60.0 fps */
min_exp_time = "13"; /* us */
max_exp_time = "683709"; /* us */
step_exp_time = "1";
default_exp_time = "16667"; /* us */
};
mode1 { // E2832_3840x2160
mclk_khz = "24000";
num_lanes = "8";
tegra_sinterface = "serial_a";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "3840";
active_h = "2160";
mode_type = "rgb";
pixel_phase = "rgb888";
csi_pixel_bit_depth = "24";
readout_orientation = "0";
line_length = "3840";
inherent_gain = "1";
mclk_multiplier = "24";
pix_clk_hz = "500000000";
gain_factor = "16";
framerate_factor = "1000000";
exposure_factor = "1000000";
min_gain_val = "16"; /* 1.00x */
max_gain_val = "170"; /* 10.66x */
step_gain_val = "1";
default_gain = "16"; /* 1.00x */
min_hdr_ratio = "1";
max_hdr_ratio = "1";
min_framerate = "2000000"; /* 2.0 fps */
max_framerate = "60000000"; /* 60.0 fps */
step_framerate = "1";
default_framerate = "60000000"; /* 60.0 fps */
min_exp_time = "13"; /* us */
max_exp_time = "683709"; /* us */
step_exp_time = "1";
default_exp_time = "16667"; /* us */
};
mode2 { // E2832_1280x720_60Fps
mclk_khz = "24000";
num_lanes = "4";
tegra_sinterface = "serial_a";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
mode_type = "rgb";
pixel_phase = "rgb888";
csi_pixel_bit_depth = "24";
readout_orientation = "0";
line_length = "1280";
inherent_gain = "1";
mclk_multiplier = "24";
pix_clk_hz = "250000000";
gain_factor = "16";
framerate_factor = "1000000";
exposure_factor = "1000000";
min_gain_val = "16"; /* 1.00x */
max_gain_val = "170"; /* 10.66x */
step_gain_val = "1";
default_gain = "16"; /* 1.00x */
min_hdr_ratio = "1";
max_hdr_ratio = "1";
min_framerate = "2000000"; /* 2.0 fps */
max_framerate = "60000000"; /* 60.0 fps */
step_framerate = "1";
default_framerate = "60000000"; /* 60.0 fps */
min_exp_time = "13"; /* us */
max_exp_time = "683709"; /* us */
step_exp_time = "1";
default_exp_time = "16667"; /* us */
};
ports { ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@0 { port@0 {
reg = <0>; reg = <0>;
p3785_vi_in0: endpoint { p3785_out0: endpoint {
port-index = <0>; port-index = <0>;
bus-width = <8>; bus-width = <8>;
remote-endpoint = <&p3785_csi_out0>; remote-endpoint = <&p3785_csi_in0>;
}; };
}; };
}; };
}; };
bus@0 {
host1x@13e00000 {
nvcsi@15a00000 {
num-channels = <1>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
p3785_csi_in0: endpoint@0 {
port-index = <0>;
bus-width = <8>;
remote-endpoint = <&p3785_out0>;
};
};
port@1 {
reg = <1>;
p3785_csi_out0: endpoint@1 {
remote-endpoint = <&p3785_vi_in0>;
};
};
};
};
};
};
i2c@3180000 {
p3785@56 {
compatible = "nvidia,lt6911uxc";
/* I2C device address */
reg = <0x56>;
/* V4L2 device node location */
devnode = "video0";
/* Physical dimensions of sensor */
physical_w = "3.674";
physical_h = "2.738";
sensor_model = "p3785";
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources
avdd-reg = "vana";
iovdd-reg = "vif";
dvdd-reg = "vdig";*/
/* Defines number of frames to be dropped by driver internally after applying */
/* sensor crop settings. Some sensors send corrupt frames after applying */
/* crop co-ordinates */
/*post_crop_frame_drop = "0";*/
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
reset-gpios = <&gpio_aon CAM0_PWDN GPIO_ACTIVE_HIGH>;
/**
* ==== Modes ====
* A modeX node is required to support v4l2 driver
* implementation with NVIDIA camera software stack
*
* == Signal properties ==
*
* phy_mode = "";
* PHY mode used by the MIPI lanes for this device
*
* tegra_sinterface = "";
* CSI Serial interface connected to tegra
* Incase of virtual HW devices, use virtual
* For SW emulated devices, use host
*
* pix_clk_hz = "";
* Sensor pixel clock used for calculations like exposure and framerate
*
* readout_orientation = "0";
* Based on camera module orientation.
* Only change readout_orientation if you specifically
* Program a different readout order for this mode
*
* == Image format Properties ==
*
* active_w = "";
* Pixel active region width
*
* active_h = "";
* Pixel active region height
*
* pixel_t = "";
* The sensor readout pixel pattern
*
* line_length = "";
* Pixel line length (width) for sensor mode.
*
* == Source Control Settings ==
*
* Gain factor used to convert fixed point integer to float
* Gain range [min_gain/gain_factor, max_gain/gain_factor]
* Gain step [step_gain/gain_factor is the smallest step that can be configured]
* Default gain [Default gain to be initialized for the control.
* use min_gain_val as default for optimal results]
* Framerate factor used to convert fixed point integer to float
* Framerate range [min_framerate/framerate_factor, max_framerate/framerate_factor]
* Framerate step [step_framerate/framerate_factor is the smallest step that can be configured]
* Default Framerate [Default framerate to be initialized for the control.
* use max_framerate to get required performance]
* Exposure factor used to convert fixed point integer to float
* For convenience use 1 sec = 1000000us as conversion factor
* Exposure range [min_exp_time/exposure_factor, max_exp_time/exposure_factor]
* Exposure step [step_exp_time/exposure_factor is the smallest step that can be configured]
* Default Exposure Time [Default exposure to be initialized for the control.
* Set default exposure based on the default_framerate for optimal exposure settings]
* For convenience use 1 sec = 1000000us as conversion factor
*
* gain_factor = ""; (integer factor used for floating to fixed point conversion)
* min_gain_val = ""; (ceil to integer)
* max_gain_val = ""; (ceil to integer)
* step_gain_val = ""; (ceil to integer)
* default_gain = ""; (ceil to integer)
* Gain limits for mode
*
* exposure_factor = ""; (integer factor used for floating to fixed point conversion)
* min_exp_time = ""; (ceil to integer)
* max_exp_time = ""; (ceil to integer)
* step_exp_time = ""; (ceil to integer)
* default_exp_time = ""; (ceil to integer)
* Exposure Time limits for mode (sec)
*
* framerate_factor = ""; (integer factor used for floating to fixed point conversion)
* min_framerate = ""; (ceil to integer)
* max_framerate = ""; (ceil to integer)
* step_framerate = ""; (ceil to integer)
* default_framerate = ""; (ceil to integer)
* Framerate limits for mode (fps)
*
* embedded_metadata_height = "";
* Sensor embedded metadata height in units of rows.
* If sensor does not support embedded metadata value should be 0.
* num_of_exposure = "";
* Digital overlap(Dol) frames
*
* num_of_ignored_lines = "";
* Used for cropping, eg. OB lines + Ignored area of effective pixel lines
*
* num_of_lines_offset_0 = "";
* Used for cropping, vertical blanking in front of short exposure data
* If more Dol frames are used, it can be extended, eg. num_of_lines_offset_1
*
* num_of_ignored_pixels = "";
* Used for cropping, The length of line info(pixels)
*
* num_of_left_margin_pixels = "";
* Used for cropping, the size of the left edge margin before
* the active pixel area (after ignored pixels)
*
* num_of_right_margin_pixels = "";
* Used for cropping, the size of the right edge margin after
* the active pixel area
*
*/
mode0 { // E2832_1920x1080_60Fps
mclk_khz = "24000";
num_lanes = "4";
tegra_sinterface = "serial_a";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1920";
active_h = "1080";
mode_type = "rgb";
pixel_phase = "rgb888";
csi_pixel_bit_depth = "24";
readout_orientation = "0";
line_length = "1920";
inherent_gain = "1";
mclk_multiplier = "24";
pix_clk_hz = "250000000";
gain_factor = "16";
framerate_factor = "1000000";
exposure_factor = "1000000";
min_gain_val = "16"; /* 1.00x */
max_gain_val = "170"; /* 10.66x */
step_gain_val = "1";
default_gain = "16"; /* 1.00x */
min_hdr_ratio = "1";
max_hdr_ratio = "1";
min_framerate = "2000000"; /* 2.0 fps */
max_framerate = "60000000"; /* 60.0 fps */
step_framerate = "1";
default_framerate = "60000000"; /* 60.0 fps */
min_exp_time = "13"; /* us */
max_exp_time = "683709"; /* us */
step_exp_time = "1";
default_exp_time = "16667"; /* us */
};
mode1 { // E2832_3840x2160
mclk_khz = "24000";
num_lanes = "8";
tegra_sinterface = "serial_a";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "3840";
active_h = "2160";
mode_type = "rgb";
pixel_phase = "rgb888";
csi_pixel_bit_depth = "24";
readout_orientation = "0";
line_length = "3840";
inherent_gain = "1";
mclk_multiplier = "24";
pix_clk_hz = "500000000";
gain_factor = "16";
framerate_factor = "1000000";
exposure_factor = "1000000";
min_gain_val = "16"; /* 1.00x */
max_gain_val = "170"; /* 10.66x */
step_gain_val = "1";
default_gain = "16"; /* 1.00x */
min_hdr_ratio = "1";
max_hdr_ratio = "1";
min_framerate = "2000000"; /* 2.0 fps */
max_framerate = "60000000"; /* 60.0 fps */
step_framerate = "1";
default_framerate = "60000000"; /* 60.0 fps */
min_exp_time = "13"; /* us */
max_exp_time = "683709"; /* us */
step_exp_time = "1";
default_exp_time = "16667"; /* us */
};
mode2 { // E2832_1280x720_60Fps
mclk_khz = "24000";
num_lanes = "4";
tegra_sinterface = "serial_a";
phy_mode = "DPHY";
discontinuous_clk = "yes";
dpcm_enable = "false";
cil_settletime = "0";
active_w = "1280";
active_h = "720";
mode_type = "rgb";
pixel_phase = "rgb888";
csi_pixel_bit_depth = "24";
readout_orientation = "0";
line_length = "1280";
inherent_gain = "1";
mclk_multiplier = "24";
pix_clk_hz = "250000000";
gain_factor = "16";
framerate_factor = "1000000";
exposure_factor = "1000000";
min_gain_val = "16"; /* 1.00x */
max_gain_val = "170"; /* 10.66x */
step_gain_val = "1";
default_gain = "16"; /* 1.00x */
min_hdr_ratio = "1";
max_hdr_ratio = "1";
min_framerate = "2000000"; /* 2.0 fps */
max_framerate = "60000000"; /* 60.0 fps */
step_framerate = "1";
default_framerate = "60000000"; /* 60.0 fps */
min_exp_time = "13"; /* us */
max_exp_time = "683709"; /* us */
step_exp_time = "1";
default_exp_time = "16667"; /* us */
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
p3785_out0: endpoint {
port-index = <0>;
bus-width = <8>;
remote-endpoint = <&p3785_csi_in0>;
};
};
};
};
};
};
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <4>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <750000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. "rear" or "front".
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*/
modules {
module0 {
badge = "p3785_ltx6911";
position = "bottom";
orientation = "1";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Declare the device-tree hierarchy to driver instance */
sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/p3785@56";
};
};
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
tegra-camera-platform {
compatible = "nvidia, tegra-camera-platform";
/**
* Physical settings to calculate max ISO BW
*
* num_csi_lanes = <>;
* Total number of CSI lanes when all cameras are active
*
* max_lane_speed = <>;
* Max lane speed in Kbit/s
*
* min_bits_per_pixel = <>;
* Min bits per pixel
*
* vi_peak_byte_per_pixel = <>;
* Max byte per pixel for the VI ISO case
*
* vi_bw_margin_pct = <>;
* Vi bandwidth margin in percentage
*
* max_pixel_rate = <>;
* Max pixel rate in Kpixel/s for the ISP ISO case
*
* isp_peak_byte_per_pixel = <>;
* Max byte per pixel for the ISP ISO case
*
* isp_bw_margin_pct = <>;
* Isp bandwidth margin in percentage
*/
num_csi_lanes = <4>;
max_lane_speed = <1500000>;
min_bits_per_pixel = <10>;
vi_peak_byte_per_pixel = <2>;
vi_bw_margin_pct = <25>;
max_pixel_rate = <750000>;
isp_peak_byte_per_pixel = <5>;
isp_bw_margin_pct = <25>;
/**
* The general guideline for naming badge_info contains 3 parts, and is as follows,
* The first part is the camera_board_id for the module; if the module is in a FFD
* platform, then use the platform name for this part.
* The second part contains the position of the module, ex. "rear" or "front".
* The third part contains the last 6 characters of a part number which is found
* in the module's specsheet from the vender.
*/
modules {
module0 {
badge = "p3785_ltx6911";
position = "bottom";
orientation = "1";
drivernode0 {
/* Declare PCL support driver (classically known as guid) */
pcl_id = "v4l2_sensor";
/* Declare the device-tree hierarchy to driver instance */
sysfs-device-tree = "/sys/firmware/devicetree/base/bus@0/i2c@3180000/p3785@56";
};
};
};
};
}; };

1065
nv-platform/tegra234-dcb-p3737-0000-p3701-0000.dtsi
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485
nv-platform/tegra234-p3701-0000-prod-overlay.dtsi
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@@ -2,256 +2,247 @@
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX bus@0 {
fragment-p3701-prod@0 { aon@c000000 {
target-path = "/"; prod-settings {
__overlay__ { #prod-cells = <4>;
#endif prod {
bus@0 { board {
aon@c000000 { prod = <
prod-settings { 0 0x00260004 0x0000003f 0x00000020>; //SPI_COMMAND2_0
#prod-cells = <4>; };
prod { };
board { };
prod = < };
0 0x00260004 0x0000003f 0x00000020>; //SPI_COMMAND2_0
}; i2c@3160000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod_c_fm {
board {
i2c@3160000 { prod = <
prod-settings { 0 0x0000006c 0xffff0000 0x003c0000 //I2C_I2C_CLK_DIVISOR_REGISTER_0
#prod-cells = <4>; 0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0
prod_c_fm { 0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
board { };
prod = < };
0 0x0000006c 0xffff0000 0x003c0000 //I2C_I2C_CLK_DIVISOR_REGISTER_0 prod_c_fmplus {
0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0 board {
0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0 prod = <
}; 0 0x0000006c 0xffff0000 0x00160000 //I2C_I2C_CLK_DIVISOR_REGISTER_0
}; 0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0
prod_c_fmplus { 0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
board { };
prod = < };
0 0x0000006c 0xffff0000 0x00160000 //I2C_I2C_CLK_DIVISOR_REGISTER_0 };
0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0 };
0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
}; i2c@3180000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod_c_fmplus {
board {
i2c@3180000 { prod = <
prod-settings { 0 0x0000006c 0xffff0000 0x00160000 //I2C_I2C_CLK_DIVISOR_REGISTER_0
#prod-cells = <4>; 0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0
prod_c_fmplus { 0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
board { };
prod = < };
0 0x0000006c 0xffff0000 0x00160000 //I2C_I2C_CLK_DIVISOR_REGISTER_0 prod_c_sm {
0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0 board {
0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0 prod = <
}; 0 0x0000006c 0xffff0000 0x004f0000 //I2C_I2C_CLK_DIVISOR_REGISTER_0
}; 0 0x00000094 0x0000ffff 0x00000708 //I2C_I2C_INTERFACE_TIMING_0_0
prod_c_sm { 0 0x00000098 0xffffffff 0x08080808>; //I2C_I2C_INTERFACE_TIMING_1_0
board { };
prod = < };
0 0x0000006c 0xffff0000 0x004f0000 //I2C_I2C_CLK_DIVISOR_REGISTER_0 };
0 0x00000094 0x0000ffff 0x00000708 //I2C_I2C_INTERFACE_TIMING_0_0 };
0 0x00000098 0xffffffff 0x08080808>; //I2C_I2C_INTERFACE_TIMING_1_0
}; i2c@3190000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod_c_fm {
board {
i2c@3190000 { prod = <
prod-settings { 0 0x0000006c 0xffff0000 0x003c0000 //I2C_I2C_CLK_DIVISOR_REGISTER_0
#prod-cells = <4>; 0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0
prod_c_fm { 0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
board { };
prod = < };
0 0x0000006c 0xffff0000 0x003c0000 //I2C_I2C_CLK_DIVISOR_REGISTER_0 };
0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0 };
0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
}; i2c@31c0000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod_c_fm {
board {
i2c@31c0000 { prod = <
prod-settings { 0 0x0000006c 0xffff0000 0x003c0000 //I2C_I2C_CLK_DIVISOR_REGISTER_0
#prod-cells = <4>; 0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0
prod_c_fm { 0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
board { };
prod = < };
0 0x0000006c 0xffff0000 0x003c0000 //I2C_I2C_CLK_DIVISOR_REGISTER_0 };
0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0 };
0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
}; i2c@31e0000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod_c_fm {
board {
i2c@31e0000 { prod = <
prod-settings { 0 0x0000006c 0xffff0000 0x003c0000 //I2C_I2C_CLK_DIVISOR_REGISTER_0
#prod-cells = <4>; 0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0
prod_c_fm { 0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
board { };
prod = < };
0 0x0000006c 0xffff0000 0x003c0000 //I2C_I2C_CLK_DIVISOR_REGISTER_0 };
0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0 };
0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
}; i2c@c240000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod_c_fmplus {
board {
i2c@c240000 { prod = <
prod-settings { 0 0x0000006c 0xffff0000 0x00160000 //I2C_I2C_CLK_DIVISOR_REGISTER_0
#prod-cells = <4>; 0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0
prod_c_fmplus { 0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
board { };
prod = < };
0 0x0000006c 0xffff0000 0x00160000 //I2C_I2C_CLK_DIVISOR_REGISTER_0 };
0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0 };
0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
}; i2c@c250000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod_c_fmplus {
board {
i2c@c250000 { prod = <
prod-settings { 0 0x0000006c 0xffff0000 0x00160000 //I2C_I2C_CLK_DIVISOR_REGISTER_0
#prod-cells = <4>; 0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0
prod_c_fmplus { 0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
board { };
prod = < };
0 0x0000006c 0xffff0000 0x00160000 //I2C_I2C_CLK_DIVISOR_REGISTER_0 };
0 0x00000094 0x0000ffff 0x00000202 //I2C_I2C_INTERFACE_TIMING_0_0 };
0 0x00000098 0xffffffff 0x02020202>; //I2C_I2C_INTERFACE_TIMING_1_0
}; mttcan@c310000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod_c_can_2m_1m {
board {
mttcan@c310000 { prod = <
prod-settings { 0 0x00000048 0x00007f00 0x00000000>; //M_TTCAN_CORE_TDCR_0
#prod-cells = <4>; };
prod_c_can_2m_1m { };
board { prod_c_can_5m {
prod = < board {
0 0x00000048 0x00007f00 0x00000000>; //M_TTCAN_CORE_TDCR_0 prod = <
}; 0 0x00000048 0x00007f00 0x00000600>; //M_TTCAN_CORE_TDCR_0
}; };
prod_c_can_5m { };
board { prod_c_can_8m {
prod = < board {
0 0x00000048 0x00007f00 0x00000600>; //M_TTCAN_CORE_TDCR_0 prod = <
}; 0 0x00000048 0x00007f00 0x00000400>; //M_TTCAN_CORE_TDCR_0
}; };
prod_c_can_8m { };
board { };
prod = < };
0 0x00000048 0x00007f00 0x00000400>; //M_TTCAN_CORE_TDCR_0
}; mttcan@c320000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod_c_can_2m_1m {
board {
mttcan@c320000 { prod = <
prod-settings { 1 0x0000f048 0x00007f00 0x00000000>; //M_TTCAN_CORE_TDCR_0
#prod-cells = <4>; };
prod_c_can_2m_1m { };
board { prod_c_can_5m {
prod = < board {
1 0x0000f048 0x00007f00 0x00000000>; //M_TTCAN_CORE_TDCR_0 prod = <
}; 1 0x0000f048 0x00007f00 0x00000600>; //M_TTCAN_CORE_TDCR_0
}; };
prod_c_can_5m { };
board { prod_c_can_8m {
prod = < board {
1 0x0000f048 0x00007f00 0x00000600>; //M_TTCAN_CORE_TDCR_0 prod = <
}; 1 0x0000f048 0x00007f00 0x00000400>; //M_TTCAN_CORE_TDCR_0
}; };
prod_c_can_8m { };
board { };
prod = < };
1 0x0000f048 0x00007f00 0x00000400>; //M_TTCAN_CORE_TDCR_0
}; spi@3210000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod {
board {
spi@3210000 { prod = <
prod-settings { 0 0x00000004 0x0000003f 0x00000030>; //SPI_COMMAND2_0
#prod-cells = <4>; };
prod { };
board { };
prod = < };
0 0x00000004 0x0000003f 0x00000030>; //SPI_COMMAND2_0
}; spi@3230000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod {
board {
spi@3230000 { prod = <
prod-settings { 0 0x00000004 0x0000003f 0x00000020>; //SPI_COMMAND2_0
#prod-cells = <4>; };
prod { };
board { };
prod = < };
0 0x00000004 0x0000003f 0x00000020>; //SPI_COMMAND2_0
}; spi@3270000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod {
board {
spi@3270000 { prod = <
prod-settings { 0 0x00000004 0x00007cff 0x00000010 //QSPI_COMMAND2_0
#prod-cells = <4>; 0 0x000001ec 0x01f1f000 0x00a0a000>; //QSPI_QSPI_COMP_CONTROL_0
prod { };
board { };
prod = < };
0 0x00000004 0x00007cff 0x00000010 //QSPI_COMMAND2_0 };
0 0x000001ec 0x01f1f000 0x00a0a000>; //QSPI_QSPI_COMP_CONTROL_0
}; ufshci@2500000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod {
board {
ufshci@2500000 { prod = <
prod-settings { 0x02470000 0x00002220 0xffffffff 0x001aadb5 //MPHY_RX_APB_VENDOR3B_0
#prod-cells = <4>; 0x02480000 0x00002220 0xffffffff 0x001aadb5>; //MPHY_RX_APB_VENDOR3B_0
prod { };
board { };
prod = < };
0x02470000 0x00002220 0xffffffff 0x001aadb5 //MPHY_RX_APB_VENDOR3B_0 };
0x02480000 0x00002220 0xffffffff 0x001aadb5>; //MPHY_RX_APB_VENDOR3B_0
}; xusb_padctl@3520000 {
}; prod-settings {
}; #prod-cells = <4>;
}; prod {
board {
xusb_padctl@3520000 { prod = <
prod-settings { 0 0x00000088 0x01fe0000 0x00cc0000 //XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0
#prod-cells = <4>; 0 0x00000094 0x0000000e 0x00000004 //XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0
prod { 0 0x000000c8 0x01fe0000 0x00cc0000 //XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0
board { 0 0x000000d4 0x0000000e 0x00000004 //XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0
prod = < 0 0x00000108 0x01fe0000 0x00cc0000 //XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0
0 0x00000088 0x01fe0000 0x00cc0000 //XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0 0 0x00000114 0x0000000e 0x00000000 //XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0
0 0x00000094 0x0000000e 0x00000004 //XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0 0 0x00000148 0x01fe0000 0x00cc0000>; //XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0
0 0x000000c8 0x01fe0000 0x00cc0000 //XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0
0 0x000000d4 0x0000000e 0x00000004 //XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0
0 0x00000108 0x01fe0000 0x00cc0000 //XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0
0 0x00000114 0x0000000e 0x00000000 //XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0
0 0x00000148 0x01fe0000 0x00cc0000>; //XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0
};
};
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

265
nv-platform/tegra234-p3701-0000.dtsi
View File

@@ -4,151 +4,142 @@
#include "tegra234-p3701-0000-prod-overlay.dtsi" #include "tegra234-p3701-0000-prod-overlay.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX bus@0 {
fragment-t234-p3701-0000@0 { i2c@c240000 {
target-path = "/"; ina3221@40 {
__overlay__ { compatible = "ti,ina3221";
#endif reg = <0x40>;
bus@0 { #address-cells = <1>;
i2c@c240000 { #size-cells = <0>;
ina3221@40 { #io-channel-cells = <1>;
compatible = "ti,ina3221"; channel@0 {
reg = <0x40>; reg = <0x0>;
#address-cells = <1>; label = "VDD_GPU_SOC";
#size-cells = <0>; shunt-resistor-micro-ohms = <2000>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
label = "VDD_GPU_SOC";
shunt-resistor-micro-ohms = <2000>;
};
channel@1 {
reg = <0x1>;
label = "VDD_CPU_CV";
shunt-resistor-micro-ohms = <2000>;
};
channel@2 {
reg = <0x2>;
label = "VIN_SYS_5V0";
shunt-resistor-micro-ohms = <2000>;
summation-bypass;
};
};
ina3221@41 {
compatible = "ti,ina3221";
reg = <0x41>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
status = "disabled";
};
channel@1 {
reg = <0x1>;
label = "VDDQ_VDD2_1V8AO";
shunt-resistor-micro-ohms = <2000>;
};
channel@2 {
reg = <0x2>;
status = "disabled";
};
};
}; };
channel@1 {
spi@3270000 { reg = <0x1>;
flash@0 { label = "VDD_CPU_CV";
spi-max-frequency = <51000000>; shunt-resistor-micro-ohms = <2000>;
spi-tx-bus-width = <1>; };
spi-rx-bus-width = <1>; channel@2 {
}; reg = <0x2>;
label = "VIN_SYS_5V0";
shunt-resistor-micro-ohms = <2000>;
summation-bypass;
}; };
}; };
hdr40_vdd_3v3: regulator@3 { ina3221@41 {
compatible = "regulator-fixed"; compatible = "ti,ina3221";
reg = <3>; reg = <0x41>;
regulator-name = "vdd-3v3-sys"; #address-cells = <1>;
regulator-min-microvolt = <3300000>; #size-cells = <0>;
regulator-max-microvolt = <3300000>; #io-channel-cells = <1>;
}; channel@0 {
reg = <0x0>;
bpmp { status = "disabled";
i2c { };
vrs@3c { channel@1 {
compatible = "nvidia,vrs-pseq"; reg = <0x1>;
reg = <0x3c>; label = "VDDQ_VDD2_1V8AO";
interrupt-parent = <&pmc>; shunt-resistor-micro-ohms = <2000>;
/* VRS Wake ID is 24 */ };
interrupts = <24 IRQ_TYPE_LEVEL_LOW>; channel@2 {
interrupt-controller; reg = <0x2>;
#interrupt-cells = <2>; status = "disabled";
status = "okay";
};
tegra_tmp451: thermal-sensor@4c {
compatible = "ti,tmp451";
reg = <0x4c>;
vcc-supply = <&vdd_1v8_ao>;
#thermal-sensor-cells = <1>;
status = "okay";
};
vrs11_1@20 {
compatible = "nvidia,vrs11";
reg = <0x20>;
rail-name-loopA = "GPU";
rail-name-loopB = "CPU";
};
vrs11_2@22 {
compatible = "nvidia,vrs11";
reg = <0x22>;
rail-name-loopA = "SOC";
rail-name-loopB = "CV";
};
}; };
}; };
};
thermal-zones { spi@3270000 {
tboard-thermal { flash@0 {
polling-delay = <1000>; spi-max-frequency = <51000000>;
polling-delay-passive = <1000>; spi-tx-bus-width = <1>;
thermal-sensors = <&tegra_tmp451 0>; spi-rx-bus-width = <1>;
status = "okay";
};
tdiode-thermal {
polling-delay = <1000>;
polling-delay-passive = <1000>;
thermal-sensors = <&tegra_tmp451 1>;
status = "okay";
};
}; };
eeprom-manager {
bus@0 {
i2c-bus = <&gen1_i2c>;
eeprom@0 {
slave-address = <0x50>;
label = "cvm";
};
};
};
reserved-memory {
linux,cma { /* Needed for nvgpu comptags */
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x10000000>; /* 256MB */
alignment = <0x0 0x10000>;
linux,cma-default;
status = "okay";
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
hdr40_vdd_3v3: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "vdd-3v3-sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
bpmp {
i2c {
vrs@3c {
compatible = "nvidia,vrs-pseq";
reg = <0x3c>;
interrupt-parent = <&pmc>;
/* VRS Wake ID is 24 */
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
};
tegra_tmp451: thermal-sensor@4c {
compatible = "ti,tmp451";
reg = <0x4c>;
vcc-supply = <&vdd_1v8_ao>;
#thermal-sensor-cells = <1>;
status = "okay";
};
vrs11_1@20 {
compatible = "nvidia,vrs11";
reg = <0x20>;
rail-name-loopA = "GPU";
rail-name-loopB = "CPU";
};
vrs11_2@22 {
compatible = "nvidia,vrs11";
reg = <0x22>;
rail-name-loopA = "SOC";
rail-name-loopB = "CV";
};
};
};
thermal-zones {
tboard-thermal {
polling-delay = <1000>;
polling-delay-passive = <1000>;
thermal-sensors = <&tegra_tmp451 0>;
status = "okay";
};
tdiode-thermal {
polling-delay = <1000>;
polling-delay-passive = <1000>;
thermal-sensors = <&tegra_tmp451 1>;
status = "okay";
};
};
eeprom-manager {
bus@0 {
i2c-bus = <&gen1_i2c>;
eeprom@0 {
slave-address = <0x50>;
label = "cvm";
};
};
};
reserved-memory {
linux,cma { /* Needed for nvgpu comptags */
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x10000000>; /* 256MB */
alignment = <0x0 0x10000>;
linux,cma-default;
status = "okay";
};
};
}; };

535
nv-platform/tegra234-p3701-0008.dtsi
View File

@@ -2,290 +2,281 @@
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX bus@0 {
fragment-t234-p3701-0008@0 { i2c@c240000 {
target-path = "/"; ina3221@40 {
__overlay__ { compatible = "ti,ina3221";
#endif reg = <0x40>;
bus@0 { #address-cells = <1>;
i2c@c240000 { #size-cells = <0>;
ina3221@40 { #io-channel-cells = <1>;
compatible = "ti,ina3221"; channel@0 {
reg = <0x40>; reg = <0x0>;
#address-cells = <1>; label = "VDD_GPU_SOC";
#size-cells = <0>; shunt-resistor-micro-ohms = <2000>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
label = "VDD_GPU_SOC";
shunt-resistor-micro-ohms = <2000>;
};
channel@1 {
reg = <0x1>;
label = "VDD_CPU_CV";
shunt-resistor-micro-ohms = <2000>;
};
channel@2 {
reg = <0x2>;
label = "VIN_SYS_5V0";
shunt-resistor-micro-ohms = <2000>;
summation-bypass;
};
};
ina3221@41 {
compatible = "ti,ina3221";
reg = <0x41>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
status = "disabled";
};
channel@1 {
reg = <0x1>;
label = "VDDQ_VDD2_1V8AO";
shunt-resistor-micro-ohms = <2000>;
};
channel@2 {
reg = <0x2>;
status = "disabled";
};
};
}; };
channel@1 {
i2c@c250000 { reg = <0x1>;
ina3221@41 { label = "VDD_CPU_CV";
compatible = "ti,ina3221"; shunt-resistor-micro-ohms = <2000>;
reg = <0x41>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
label = "CVB_ATX_12V";
shunt-resistor-micro-ohms = <2000>;
};
channel@1 {
reg = <0x1>;
label = "CVB_ATX_3V3";
shunt-resistor-micro-ohms = <2000>;
};
channel@2 {
reg = <0x2>;
label = "CVB_ATX_5V";
shunt-resistor-micro-ohms = <2000>;
};
};
ina219@44 {
compatible = "ti,ina219";
reg = <0x44>;
shunt-resistor = <2000>;
label = "CVB_ATX_12V_8P";
};
}; };
channel@2 {
spi@3270000 { reg = <0x2>;
flash@0 { label = "VIN_SYS_5V0";
spi-max-frequency = <51000000>; shunt-resistor-micro-ohms = <2000>;
spi-tx-bus-width = <1>; summation-bypass;
spi-rx-bus-width = <1>;
};
}; };
}; };
bpmp { ina3221@41 {
i2c { compatible = "ti,ina3221";
vrs@3c { reg = <0x41>;
compatible = "nvidia,vrs-pseq"; #address-cells = <1>;
reg = <0x3c>; #size-cells = <0>;
interrupt-parent = <&pmc>; #io-channel-cells = <1>;
/* VRS Wake ID is 24 */ channel@0 {
interrupts = <24 IRQ_TYPE_LEVEL_LOW>; reg = <0x0>;
interrupt-controller; status = "disabled";
#interrupt-cells = <2>; };
status = "okay"; channel@1 {
}; reg = <0x1>;
label = "VDDQ_VDD2_1V8AO";
vrs11_1@20 { shunt-resistor-micro-ohms = <2000>;
compatible = "nvidia,vrs11"; };
reg = <0x20>; channel@2 {
rail-name-loopA = "GPU"; reg = <0x2>;
rail-name-loopB = "CPU"; status = "disabled";
}; };
};
vrs11_2@22 { };
compatible = "nvidia,vrs11";
reg = <0x22>;
rail-name-loopA = "SOC";
rail-name-loopB = "CV";
};
tegra_tmp451: thermal-sensor@4c {
compatible = "ti,tmp451";
reg = <0x4c>;
vcc-supply = <&vdd_1v8_ao>;
#thermal-sensor-cells = <1>;
status = "okay";
};
i2c@c250000 {
ina3221@41 {
compatible = "ti,ina3221";
reg = <0x41>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
label = "CVB_ATX_12V";
shunt-resistor-micro-ohms = <2000>;
};
channel@1 {
reg = <0x1>;
label = "CVB_ATX_3V3";
shunt-resistor-micro-ohms = <2000>;
};
channel@2 {
reg = <0x2>;
label = "CVB_ATX_5V";
shunt-resistor-micro-ohms = <2000>;
}; };
}; };
eeprom-manager { ina219@44 {
bus@0 { compatible = "ti,ina219";
i2c-bus = <&gen1_i2c>; reg = <0x44>;
eeprom@0 { shunt-resistor = <2000>;
slave-address = <0x50>; label = "CVB_ATX_12V_8P";
label = "cvm";
};
};
}; };
};
opp-table-cluster0 { spi@3270000 {
opp-1971200000 { flash@0 {
opp-hz = /bits/ 64 <1971200000>; spi-max-frequency = <51000000>;
opp-peak-kBps = <3200000>; spi-tx-bus-width = <1>;
}; spi-rx-bus-width = <1>;
}; };
opp-table-cluster1 {
opp-1971200000 {
opp-hz = /bits/ 64 <1971200000>;
opp-peak-kBps = <3200000>;
};
};
opp-table-cluster2 {
opp-1971200000 {
opp-hz = /bits/ 64 <1971200000>;
opp-peak-kBps = <3200000>;
};
};
thermal-zones {
cpu-thermal {
trips {
cpu-sw-slowdown {
temperature = <112000>;
};
cpu-sw-shutdown {
temperature = <117500>;
};
};
};
cv0-thermal {
trips {
cv0-sw-slowdown {
temperature = <112000>;
};
cv0-sw-shutdown {
temperature = <117500>;
};
};
};
cv1-thermal {
trips {
cv1-sw-slowdown {
temperature = <112000>;
};
cv1-sw-shutdown {
temperature = <117500>;
};
};
};
cv2-thermal {
trips {
cv2-sw-slowdown {
temperature = <112000>;
};
cv2-sw-shutdown {
temperature = <117500>;
};
};
};
gpu-thermal {
trips {
gpu-sw-slowdown {
temperature = <112000>;
};
gpu-sw-shutdown {
temperature = <117500>;
};
};
};
soc0-thermal {
trips {
soc0-sw-slowdown {
temperature = <112000>;
};
soc0-sw-shutdown {
temperature = <117500>;
};
};
};
soc1-thermal {
trips {
soc1-sw-slowdown {
temperature = <112000>;
};
soc1-sw-shutdown {
temperature = <117500>;
};
};
};
soc2-thermal {
trips {
soc2-sw-slowdown {
temperature = <112000>;
};
soc2-sw-shutdown {
temperature = <117500>;
};
};
};
tj-thermal {
trips {
tj-sw-shutdown {
temperature = <117500>;
};
};
};
tboard-thermal {
polling-delay = <1000>;
polling-delay-passive = <1000>;
thermal-sensors = <&tegra_tmp451 0>;
status = "okay";
};
tdiode-thermal {
polling-delay = <1000>;
polling-delay-passive = <1000>;
thermal-sensors = <&tegra_tmp451 1>;
status = "okay";
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
bpmp {
i2c {
vrs@3c {
compatible = "nvidia,vrs-pseq";
reg = <0x3c>;
interrupt-parent = <&pmc>;
/* VRS Wake ID is 24 */
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
};
vrs11_1@20 {
compatible = "nvidia,vrs11";
reg = <0x20>;
rail-name-loopA = "GPU";
rail-name-loopB = "CPU";
};
vrs11_2@22 {
compatible = "nvidia,vrs11";
reg = <0x22>;
rail-name-loopA = "SOC";
rail-name-loopB = "CV";
};
tegra_tmp451: thermal-sensor@4c {
compatible = "ti,tmp451";
reg = <0x4c>;
vcc-supply = <&vdd_1v8_ao>;
#thermal-sensor-cells = <1>;
status = "okay";
};
};
};
eeprom-manager {
bus@0 {
i2c-bus = <&gen1_i2c>;
eeprom@0 {
slave-address = <0x50>;
label = "cvm";
};
};
};
opp-table-cluster0 {
opp-1971200000 {
opp-hz = /bits/ 64 <1971200000>;
opp-peak-kBps = <3200000>;
};
};
opp-table-cluster1 {
opp-1971200000 {
opp-hz = /bits/ 64 <1971200000>;
opp-peak-kBps = <3200000>;
};
};
opp-table-cluster2 {
opp-1971200000 {
opp-hz = /bits/ 64 <1971200000>;
opp-peak-kBps = <3200000>;
};
};
thermal-zones {
cpu-thermal {
trips {
cpu-sw-slowdown {
temperature = <112000>;
};
cpu-sw-shutdown {
temperature = <117500>;
};
};
};
cv0-thermal {
trips {
cv0-sw-slowdown {
temperature = <112000>;
};
cv0-sw-shutdown {
temperature = <117500>;
};
};
};
cv1-thermal {
trips {
cv1-sw-slowdown {
temperature = <112000>;
};
cv1-sw-shutdown {
temperature = <117500>;
};
};
};
cv2-thermal {
trips {
cv2-sw-slowdown {
temperature = <112000>;
};
cv2-sw-shutdown {
temperature = <117500>;
};
};
};
gpu-thermal {
trips {
gpu-sw-slowdown {
temperature = <112000>;
};
gpu-sw-shutdown {
temperature = <117500>;
};
};
};
soc0-thermal {
trips {
soc0-sw-slowdown {
temperature = <112000>;
};
soc0-sw-shutdown {
temperature = <117500>;
};
};
};
soc1-thermal {
trips {
soc1-sw-slowdown {
temperature = <112000>;
};
soc1-sw-shutdown {
temperature = <117500>;
};
};
};
soc2-thermal {
trips {
soc2-sw-slowdown {
temperature = <112000>;
};
soc2-sw-shutdown {
temperature = <117500>;
};
};
};
tj-thermal {
trips {
tj-sw-shutdown {
temperature = <117500>;
};
};
};
tboard-thermal {
polling-delay = <1000>;
polling-delay-passive = <1000>;
thermal-sensors = <&tegra_tmp451 0>;
status = "okay";
};
tdiode-thermal {
polling-delay = <1000>;
polling-delay-passive = <1000>;
thermal-sensors = <&tegra_tmp451 1>;
status = "okay";
};
};
}; };

1
nv-platform/tegra234-p3737-0000+p3701-0000-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "tegra234-p3737-0000+p3701-0000.dts" #include "tegra234-p3737-0000+p3701-0000.dts"
#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi" #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3737-0000+p3701-0004-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3737-0000+p3701-0004.dts" #include "staging/tegra234-p3737-0000+p3701-0004.dts"
#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi" #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3737-0000+p3701-0005-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3737-0000+p3701-0005.dts" #include "staging/tegra234-p3737-0000+p3701-0005.dts"
#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi" #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3737-0000+p3701-0008-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3737-0000+p3701-0008.dts" #include "staging/tegra234-p3737-0000+p3701-0008.dts"
#include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi" #include "tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi"

632
nv-platform/tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi
View File

@@ -12,329 +12,319 @@
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi" #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX cpus {
compatible = "nvidia,p3737-0000+p3701-0000"; idle-states {
fragment-t234-p3737-p3701@0 { c7 {
target-path = "/";
__overlay__ {
#endif
cpus {
idle-states {
c7 {
status = "okay";
};
};
};
nvpmodel {
status = "okay"; status = "okay";
}; };
scf-pmu {
status = "okay";
};
soctherm-oc-event {
status = "okay";
};
thermal-zones {
cpu-thermal {
status = "okay";
};
cv0-thermal {
status = "okay";
};
cv1-thermal {
status = "okay";
};
cv2-thermal {
status = "okay";
};
gpu-thermal {
status = "okay";
};
soc0-thermal {
status = "okay";
};
soc1-thermal {
status = "okay";
};
soc2-thermal {
status = "okay";
};
};
bus@0 {
smmu_test {
compatible = "nvidia,smmu_test";
iommus = <&smmu_niso0 TEGRA234_SID_SMMU_TEST>;
status = "okay";
};
pinmux@2430000 {
status = "okay";
};
ufshci@2500000 {
status = "okay";
};
aconnect@2900000 {
ahub@2900800 {
i2s@2901200 {
status = "okay";
};
i2s@2901400 {
status = "okay";
};
dmic@2904000 {
status = "okay";
};
dmic@2904100 {
status = "okay";
};
dmic@2904300 {
status = "okay";
};
dspk@2905000 {
status = "okay";
};
dspk@2905100 {
status = "okay";
};
afc@2907000 {
status = "okay";
};
afc@2907100 {
status = "okay";
};
afc@2907200 {
status = "okay";
};
afc@2907300 {
status = "okay";
};
afc@2907400 {
status = "okay";
};
afc@2907500 {
status = "okay";
};
arad@290e400 {
status = "okay";
};
};
};
serial@3110000 {
compatible = "nvidia,tegra194-hsuart";
reset-names = "serial";
status = "okay";
};
i2c@3180000 {
status = "okay";
};
i2c@3190000 {
status = "okay";
};
i2c@31b0000 {
nvidia,hw-instance-id = <0x5>;
status = "okay";
};
i2c@31c0000 {
status = "okay";
};
serial@31d0000 {
current-speed = <115200>;
};
i2c@31e0000 {
status = "okay";
};
tachometer@39c0000 {
status = "okay";
};
hsp@3d00000 {
status = "okay";
};
ethernet@6800000 {
status = "okay";
};
aon@c000000 {
status = "okay";
};
hardware-timestamp@c1e0000 {
status = "okay";
nvidia,num-slices = <3>;
};
i2c@c240000 {
status = "okay";
};
hdr40_i2c1: i2c@c250000 {
status = "okay";
};
rtc@c2a0000 {
status = "okay";
};
mttcan@c310000 {
status = "okay";
};
mttcan@c320000 {
status = "okay";
};
actmon@d230000 {
status = "okay";
};
hwpm@f100000 {
status = "okay";
};
mc-hwpm@2c10000 {
status = "okay";
};
host1x@13e00000 {
nvjpg@15380000 {
status = "okay";
};
nvdec@15480000 {
status = "okay";
};
nvenc@154c0000 {
status = "okay";
};
tsec@15500000 {
status = "okay";
};
nvjpg@15540000 {
status = "okay";
};
se@15810000 {
status = "okay";
};
se@15820000 {
status = "okay";
};
se@15840000 {
status = "okay";
};
nvdla0@15880000 {
status = "okay";
};
nvdla1@158c0000 {
status = "okay";
};
ofa@15a50000 {
status = "okay";
};
pva0@16000000 {
status = "okay";
pva0_niso1_ctx0 {
status = "okay";
};
pva0_niso1_ctx1 {
status = "okay";
};
pva0_niso1_ctx2 {
status = "okay";
};
pva0_niso1_ctx3 {
status = "okay";
};
pva0_niso1_ctx4 {
status = "okay";
};
pva0_niso1_ctx5 {
status = "okay";
};
pva0_niso1_ctx6 {
status = "okay";
};
pva0_niso1_ctx7 {
status = "okay";
};
};
};
gpu@17000000 {
status = "okay";
};
};
tegra-hsp@b950000 {
status = "okay";
};
dce@d800000 {
status = "okay";
};
tegra_mce@e100000 {
status = "okay";
};
display@13800000 {
status = "okay";
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
nvpmodel {
status = "okay";
};
scf-pmu {
status = "okay";
};
soctherm-oc-event {
status = "okay";
};
thermal-zones {
cpu-thermal {
status = "okay";
};
cv0-thermal {
status = "okay";
};
cv1-thermal {
status = "okay";
};
cv2-thermal {
status = "okay";
};
gpu-thermal {
status = "okay";
};
soc0-thermal {
status = "okay";
};
soc1-thermal {
status = "okay";
};
soc2-thermal {
status = "okay";
};
};
bus@0 {
smmu_test {
compatible = "nvidia,smmu_test";
iommus = <&smmu_niso0 TEGRA234_SID_SMMU_TEST>;
status = "okay";
};
pinmux@2430000 {
status = "okay";
};
ufshci@2500000 {
status = "okay";
};
aconnect@2900000 {
ahub@2900800 {
i2s@2901200 {
status = "okay";
};
i2s@2901400 {
status = "okay";
};
dmic@2904000 {
status = "okay";
};
dmic@2904100 {
status = "okay";
};
dmic@2904300 {
status = "okay";
};
dspk@2905000 {
status = "okay";
};
dspk@2905100 {
status = "okay";
};
afc@2907000 {
status = "okay";
};
afc@2907100 {
status = "okay";
};
afc@2907200 {
status = "okay";
};
afc@2907300 {
status = "okay";
};
afc@2907400 {
status = "okay";
};
afc@2907500 {
status = "okay";
};
arad@290e400 {
status = "okay";
};
};
};
serial@3110000 {
compatible = "nvidia,tegra194-hsuart";
reset-names = "serial";
status = "okay";
};
i2c@3180000 {
status = "okay";
};
i2c@3190000 {
status = "okay";
};
i2c@31b0000 {
nvidia,hw-instance-id = <0x5>;
status = "okay";
};
i2c@31c0000 {
status = "okay";
};
serial@31d0000 {
current-speed = <115200>;
};
i2c@31e0000 {
status = "okay";
};
tachometer@39c0000 {
status = "okay";
};
hsp@3d00000 {
status = "okay";
};
ethernet@6800000 {
status = "okay";
};
aon@c000000 {
status = "okay";
};
hardware-timestamp@c1e0000 {
status = "okay";
nvidia,num-slices = <3>;
};
i2c@c240000 {
status = "okay";
};
hdr40_i2c1: i2c@c250000 {
status = "okay";
};
rtc@c2a0000 {
status = "okay";
};
mttcan@c310000 {
status = "okay";
};
mttcan@c320000 {
status = "okay";
};
actmon@d230000 {
status = "okay";
};
hwpm@f100000 {
status = "okay";
};
mc-hwpm@2c10000 {
status = "okay";
};
host1x@13e00000 {
nvjpg@15380000 {
status = "okay";
};
nvdec@15480000 {
status = "okay";
};
nvenc@154c0000 {
status = "okay";
};
tsec@15500000 {
status = "okay";
};
nvjpg@15540000 {
status = "okay";
};
se@15810000 {
status = "okay";
};
se@15820000 {
status = "okay";
};
se@15840000 {
status = "okay";
};
nvdla0@15880000 {
status = "okay";
};
nvdla1@158c0000 {
status = "okay";
};
ofa@15a50000 {
status = "okay";
};
pva0@16000000 {
status = "okay";
pva0_niso1_ctx0 {
status = "okay";
};
pva0_niso1_ctx1 {
status = "okay";
};
pva0_niso1_ctx2 {
status = "okay";
};
pva0_niso1_ctx3 {
status = "okay";
};
pva0_niso1_ctx4 {
status = "okay";
};
pva0_niso1_ctx5 {
status = "okay";
};
pva0_niso1_ctx6 {
status = "okay";
};
pva0_niso1_ctx7 {
status = "okay";
};
};
};
gpu@17000000 {
status = "okay";
};
};
tegra-hsp@b950000 {
status = "okay";
};
dce@d800000 {
status = "okay";
};
tegra_mce@e100000 {
status = "okay";
};
display@13800000 {
status = "okay";
};
}; };

221
nv-platform/tegra234-p3737-0000.dtsi
View File

@@ -2,133 +2,124 @@
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX bus@0 {
fragment-t234-p3737-0000@0 { spi@3210000{ /* SPI1 in 40 pin conn */
target-path = "/"; spi@0 { /* chip select 0 */
__overlay__ { compatible = "tegra-spidev";
#endif reg = <0x0>;
bus@0 { spi-max-frequency = <50000000>;
spi@3210000{ /* SPI1 in 40 pin conn */ };
spi@0 { /* chip select 0 */ spi@1 { /* chips select 1 */
compatible = "tegra-spidev"; compatible = "tegra-spidev";
reg = <0x0>; reg = <0x1>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
}; };
spi@1 { /* chips select 1 */ };
compatible = "tegra-spidev";
reg = <0x1>;
spi-max-frequency = <50000000>;
};
};
spi@3230000{ /* SPI3 in 40 pin conn */ spi@3230000{ /* SPI3 in 40 pin conn */
spi@0 { /* chip select 0 */ spi@0 { /* chip select 0 */
compatible = "tegra-spidev"; compatible = "tegra-spidev";
reg = <0x0>; reg = <0x0>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
}; };
spi@1 { /* chips select 1 */ spi@1 { /* chips select 1 */
compatible = "tegra-spidev"; compatible = "tegra-spidev";
reg = <0x1>; reg = <0x1>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
}; };
}; };
padctl@3520000 { padctl@3520000 {
ports {
usb2-0 {
mode = "otg";
usb-role-switch;
};
};
};
aconnect@2900000 {
ahub@2900800 {
i2s@2901100 {
ports { ports {
usb2-0 { port@1 {
mode = "otg"; hdr40_snd_i2s_dap_ep: endpoint {
usb-role-switch;
};
};
};
aconnect@2900000 {
ahub@2900800 {
i2s@2901100 {
ports {
port@1 {
hdr40_snd_i2s_dap_ep: endpoint {
};
};
}; };
}; };
}; };
}; };
};
};
ethernet@6800000 { ethernet@6800000 {
nvidia,mac-addr-idx = <0>; nvidia,mac-addr-idx = <0>;
nvidia,max-platform-mtu = <16383>; nvidia,max-platform-mtu = <16383>;
/* 1=enable, 0=disable */ /* 1=enable, 0=disable */
nvidia,pause_frames = <1>; nvidia,pause_frames = <1>;
phy-handle = <&mgbe0_aqr113c_phy>; phy-handle = <&mgbe0_aqr113c_phy>;
phy-mode = "10gbase-r"; phy-mode = "10gbase-r";
/* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */ /* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */
nvidia,phy-iface-mode = <0>; nvidia,phy-iface-mode = <0>;
nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(Y, 1) 0>; nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(Y, 1) 0>;
nvidia,mdio_addr = <0>; nvidia,mdio_addr = <0>;
mdio { mdio {
compatible = "nvidia,eqos-mdio"; compatible = "nvidia,eqos-mdio";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
mgbe0_aqr113c_phy: phy@0 { mgbe0_aqr113c_phy: phy@0 {
compatible = "ethernet-phy-ieee802.3-c45"; compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>; reg = <0x0>;
nvidia,phy-rst-pdelay-msec = <150>; /* msec */ nvidia,phy-rst-pdelay-msec = <150>; /* msec */
nvidia,phy-rst-duration-usec = <221000>; /* usec */ nvidia,phy-rst-duration-usec = <221000>; /* usec */
interrupt-parent = <&gpio>; interrupt-parent = <&gpio>;
interrupts = <TEGRA234_MAIN_GPIO(Y, 3) IRQ_TYPE_LEVEL_LOW>; interrupts = <TEGRA234_MAIN_GPIO(Y, 3) IRQ_TYPE_LEVEL_LOW>;
};
};
}; };
}; };
tegra_sound_graph: tegra_sound: sound {
compatible = "nvidia,tegra186-audio-graph-card",
"nvidia,tegra186-ape";
clocks = <&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLA_OUT0>,
<&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "pll_a", "plla_out0", "extern1";
assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
nvidia-audio-card,name = "NVIDIA Jetson AGX Orin APE";
nvidia-audio-card,mclk-fs = <256>;
hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { };
};
eeprom-manager {
data-size = <0x100>;
bus@0 {
i2c-bus = <&gen1_i2c>;
eeprom@1 {
slave-address = <0x56>;
label = "cvb";
};
};
bus@1 {
i2c-bus = <&cam_i2c>;
eeprom@0 {
slave-address = <0x54>;
label = "sensor0";
};
eeprom@1 {
slave-address = <0x57>;
label = "sensor1";
};
eeprom@2 {
slave-address = <0x52>;
label = "sensor2";
};
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
tegra_sound_graph: tegra_sound: sound {
compatible = "nvidia,tegra186-audio-graph-card",
"nvidia,tegra186-ape";
clocks = <&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLA_OUT0>,
<&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "pll_a", "plla_out0", "extern1";
assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
nvidia-audio-card,name = "NVIDIA Jetson AGX Orin APE";
nvidia-audio-card,mclk-fs = <256>;
hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { };
};
eeprom-manager {
data-size = <0x100>;
bus@0 {
i2c-bus = <&gen1_i2c>;
eeprom@1 {
slave-address = <0x56>;
label = "cvb";
};
};
bus@1 {
i2c-bus = <&cam_i2c>;
eeprom@0 {
slave-address = <0x54>;
label = "sensor0";
};
eeprom@1 {
slave-address = <0x57>;
label = "sensor1";
};
eeprom@2 {
slave-address = <0x52>;
label = "sensor2";
};
};
};
}; };

549
nv-platform/tegra234-p3740-0002+p3701-0008-nv-common.dtsi
View File

@@ -12,287 +12,276 @@
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi" #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX chosen {
compatible = "nvidia,p3740-0002+p3701-0008"; bootargs = "console=ttyTCU0,115200n8";
};
fragment-t234-p3740-p3701@0 { bpmp {
target-path = "/"; thermal {
__overlay__ { status = "okay";
#endif
chosen {
bootargs = "console=ttyTCU0,115200n8";
};
bpmp {
thermal {
status = "okay";
};
};
cpus {
idle-states {
c7 {
status = "okay";
};
};
};
nvpmodel {
status = "okay";
};
soctherm-oc-event {
status = "okay";
};
thermal-zones {
cpu-thermal {
status = "okay";
};
cv0-thermal {
status = "okay";
};
cv1-thermal {
status = "okay";
};
cv2-thermal {
status = "okay";
};
gpu-thermal {
status = "okay";
};
soc0-thermal {
status = "okay";
};
soc1-thermal {
status = "okay";
};
soc2-thermal {
status = "okay";
};
tj-thermal {
status = "okay";
};
};
bus@0 {
smmu_test {
compatible = "nvidia,smmu_test";
iommus = <&smmu_niso0 TEGRA234_SID_SMMU_TEST>;
status = "okay";
};
pinmux@2430000 {
status = "okay";
};
serial@3110000 {
compatible = "nvidia,tegra194-hsuart";
reset-names = "serial";
status = "okay";
};
serial@31d0000 {
status = "okay";
};
tachometer@39c0000 {
status = "okay";
};
hsp@3c00000 {
status = "okay";
};
hsp@c150000 {
status = "okay";
};
mttcan@c310000 {
status = "okay";
};
mttcan@c320000 {
status = "okay";
};
actmon@d230000 {
status = "okay";
};
hwpm@f100000 {
status = "okay";
};
aconnect@2900000 {
ahub@2900800 {
i2s@2901200 {
status = "okay";
};
i2s@2901400 {
status = "okay";
};
dmic@2904000 {
status = "okay";
};
dmic@2904100 {
status = "okay";
};
dmic@2904300 {
status = "okay";
};
dspk@2905000 {
status = "okay";
};
dspk@2905100 {
status = "okay";
};
arad@290e400 {
status = "okay";
};
afc@2907000 {
status = "okay";
};
afc@2907100 {
status = "okay";
};
afc@2907200 {
status = "okay";
};
afc@2907300 {
status = "okay";
};
afc@2907400 {
status = "okay";
};
afc@2907500 {
status = "okay";
};
};
};
host1x@13e00000 {
nvjpg@15380000 {
status = "okay";
};
nvenc@154c0000 {
status = "okay";
};
tsec@15500000 {
status = "okay";
};
nvjpg@15540000 {
status = "okay";
};
se@15810000 {
status = "okay";
};
se@15820000 {
status = "okay";
};
se@15840000 {
status = "okay";
};
nvdla0@15880000 {
status = "okay";
};
nvdla1@158c0000 {
status = "okay";
};
ofa@15a50000 {
status = "okay";
};
pva0@16000000 {
status = "okay";
pva0_niso1_ctx0 {
status = "okay";
};
pva0_niso1_ctx1 {
status = "okay";
};
pva0_niso1_ctx2 {
status = "okay";
};
pva0_niso1_ctx3 {
status = "okay";
};
pva0_niso1_ctx4 {
status = "okay";
};
pva0_niso1_ctx5 {
status = "okay";
};
pva0_niso1_ctx6 {
status = "okay";
};
pva0_niso1_ctx7 {
status = "okay";
};
};
};
gpu@17000000 {
status = "okay";
};
};
tegra-hsp@b950000 {
status = "okay";
};
dce@d800000 {
status = "okay";
};
tegra_mce@e100000 {
status = "okay";
};
display@13800000 {
status = "okay";
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
cpus {
idle-states {
c7 {
status = "okay";
};
};
};
nvpmodel {
status = "okay";
};
soctherm-oc-event {
status = "okay";
};
thermal-zones {
cpu-thermal {
status = "okay";
};
cv0-thermal {
status = "okay";
};
cv1-thermal {
status = "okay";
};
cv2-thermal {
status = "okay";
};
gpu-thermal {
status = "okay";
};
soc0-thermal {
status = "okay";
};
soc1-thermal {
status = "okay";
};
soc2-thermal {
status = "okay";
};
tj-thermal {
status = "okay";
};
};
bus@0 {
smmu_test {
compatible = "nvidia,smmu_test";
iommus = <&smmu_niso0 TEGRA234_SID_SMMU_TEST>;
status = "okay";
};
pinmux@2430000 {
status = "okay";
};
serial@3110000 {
compatible = "nvidia,tegra194-hsuart";
reset-names = "serial";
status = "okay";
};
serial@31d0000 {
status = "okay";
};
tachometer@39c0000 {
status = "okay";
};
hsp@3c00000 {
status = "okay";
};
hsp@c150000 {
status = "okay";
};
mttcan@c310000 {
status = "okay";
};
mttcan@c320000 {
status = "okay";
};
actmon@d230000 {
status = "okay";
};
hwpm@f100000 {
status = "okay";
};
aconnect@2900000 {
ahub@2900800 {
i2s@2901200 {
status = "okay";
};
i2s@2901400 {
status = "okay";
};
dmic@2904000 {
status = "okay";
};
dmic@2904100 {
status = "okay";
};
dmic@2904300 {
status = "okay";
};
dspk@2905000 {
status = "okay";
};
dspk@2905100 {
status = "okay";
};
arad@290e400 {
status = "okay";
};
afc@2907000 {
status = "okay";
};
afc@2907100 {
status = "okay";
};
afc@2907200 {
status = "okay";
};
afc@2907300 {
status = "okay";
};
afc@2907400 {
status = "okay";
};
afc@2907500 {
status = "okay";
};
};
};
host1x@13e00000 {
nvjpg@15380000 {
status = "okay";
};
nvenc@154c0000 {
status = "okay";
};
tsec@15500000 {
status = "okay";
};
nvjpg@15540000 {
status = "okay";
};
se@15810000 {
status = "okay";
};
se@15820000 {
status = "okay";
};
se@15840000 {
status = "okay";
};
nvdla0@15880000 {
status = "okay";
};
nvdla1@158c0000 {
status = "okay";
};
ofa@15a50000 {
status = "okay";
};
pva0@16000000 {
status = "okay";
pva0_niso1_ctx0 {
status = "okay";
};
pva0_niso1_ctx1 {
status = "okay";
};
pva0_niso1_ctx2 {
status = "okay";
};
pva0_niso1_ctx3 {
status = "okay";
};
pva0_niso1_ctx4 {
status = "okay";
};
pva0_niso1_ctx5 {
status = "okay";
};
pva0_niso1_ctx6 {
status = "okay";
};
pva0_niso1_ctx7 {
status = "okay";
};
};
};
gpu@17000000 {
status = "okay";
};
};
tegra-hsp@b950000 {
status = "okay";
};
dce@d800000 {
status = "okay";
};
tegra_mce@e100000 {
status = "okay";
};
display@13800000 {
status = "okay";
};
}; };

1
nv-platform/tegra234-p3740-0002+p3701-0008-nv-safety.dts
View File

@@ -3,7 +3,6 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "tegra234-p3740-0002+p3701-0008.dts" #include "tegra234-p3740-0002+p3701-0008.dts"
#include "tegra234-p3740-0002+p3701-0008-nv-common.dtsi" #include "tegra234-p3740-0002+p3701-0008-nv-common.dtsi"
#include "tegra234-p3740-0002+p3701-0008-safety.dtsi" #include "tegra234-p3740-0002+p3701-0008-safety.dtsi"

1
nv-platform/tegra234-p3740-0002+p3701-0008-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "tegra234-p3740-0002+p3701-0008.dts" #include "tegra234-p3740-0002+p3701-0008.dts"
#include "tegra234-p3740-0002+p3701-0008-nv-common.dtsi" #include "tegra234-p3740-0002+p3701-0008-nv-common.dtsi"

409
nv-platform/tegra234-p3740-0002+p3701-0008-safety.dtsi
View File

@@ -4,226 +4,217 @@
#include "nv-soc/tegra234-soc-safetyservice-fsicom.dtsi" #include "nv-soc/tegra234-soc-safetyservice-fsicom.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX compatible = "nvidia,p3740-0002+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234";
fragment-t234-p3740-p3701-safety@0 {
target-path = "/";
__overlay__ {
#endif
compatible = "nvidia,p3740-0002+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234";
bus@0 { bus@0 {
i2c@3160000 { i2c@3160000 {
nvidia,epl-reporter-id = <0x8050>; nvidia,epl-reporter-id = <0x8050>;
}; };
i2c@c240000 { i2c@c240000 {
nvidia,epl-reporter-id = <0x8051>; nvidia,epl-reporter-id = <0x8051>;
}; };
i2c@3180000 { i2c@3180000 {
nvidia,epl-reporter-id = <0x8052>; nvidia,epl-reporter-id = <0x8052>;
}; };
i2c@3190000 { i2c@3190000 {
nvidia,epl-reporter-id = <0x8053>; nvidia,epl-reporter-id = <0x8053>;
}; };
i2c@31b0000 { i2c@31b0000 {
nvidia,epl-reporter-id = <0x8054>; nvidia,epl-reporter-id = <0x8054>;
}; };
i2c@31c0000 { i2c@31c0000 {
nvidia,epl-reporter-id = <0x8056>; nvidia,epl-reporter-id = <0x8056>;
}; };
i2c@c250000 { i2c@c250000 {
nvidia,epl-reporter-id = <0x8057>; nvidia,epl-reporter-id = <0x8057>;
}; };
i2c@31e0000 { i2c@31e0000 {
nvidia,epl-reporter-id = <0x8058>; nvidia,epl-reporter-id = <0x8058>;
}; };
hsp_top2: hsp@1600000 { hsp_top2: hsp@1600000 {
status = "okay"; status = "okay";
}; };
spi@3230000 { spi@3230000 {
compatible = "nvidia,tegra186-spi-slave"; compatible = "nvidia,tegra186-spi-slave";
status = "okay"; status = "okay";
spi@0 { spi@0 {
compatible = "nvidia,tegra-spidev"; compatible = "nvidia,tegra-spidev";
reg = <0>; reg = <0>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
controller-data { controller-data {
nvidia,lsbyte-first; nvidia,lsbyte-first;
}; };
}; };
};
};
chosen {
/*
* The ideal approach for disabling rail-gating
* for GPU should be deleting the power-domains
* property in GPU node. But /delete-property/
* is not a valid syntax in the device tree
* overlay, the nvidia,tegra-joint_xpu_rail is
* specified to achieve the same as an
* alternative.
*/
nvidia,tegra-joint_xpu_rail;
};
cpus {
idle-states {
c7 {
status = "disabled";
};
};
};
fsicom_client {
status = "okay";
};
FsiComIvc {
status = "okay";
};
/* FSI<->CCPLEX Communication through DRAM Carveout demo app */
FsiComAppChConfApp1 {
compatible = "nvidia,tegra-fsicom-sampleApp1";
status = "okay";
channelid_list = <3>;
};
hsierrrptinj {
compatible = "nvidia,tegra23x-hsierrrptinj";
mboxes = <&hsp_top0 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(1)>;
mbox-names = "hsierrrptinj-tx";
status = "okay";
};
safetyservices_epl_client {
/* userspace app uses this driver to send error code */
status = "okay";
};
thermal-zones {
cpu-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
gpu-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
cv0-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
cv1-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
cv2-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
soc0-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
soc1-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
soc2-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
}; };
}; };
chosen {
/*
* The ideal approach for disabling rail-gating
* for GPU should be deleting the power-domains
* property in GPU node. But /delete-property/
* is not a valid syntax in the device tree
* overlay, the nvidia,tegra-joint_xpu_rail is
* specified to achieve the same as an
* alternative.
*/
nvidia,tegra-joint_xpu_rail;
};
cpus {
idle-states {
c7 {
status = "disabled";
};
};
};
fsicom_client {
status = "okay";
};
FsiComIvc {
status = "okay";
};
/* FSI<->CCPLEX Communication through DRAM Carveout demo app */
FsiComAppChConfApp1 {
compatible = "nvidia,tegra-fsicom-sampleApp1";
status = "okay";
channelid_list = <3>;
};
hsierrrptinj {
compatible = "nvidia,tegra23x-hsierrrptinj";
mboxes = <&hsp_top0 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(1)>;
mbox-names = "hsierrrptinj-tx";
status = "okay";
};
safetyservices_epl_client {
/* userspace app uses this driver to send error code */
status = "okay";
};
thermal-zones {
cpu-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
gpu-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
cv0-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
cv1-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
cv2-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
soc0-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
soc1-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
soc2-thermal {
cooling-maps {
map-cpufreq {
cooling-device = <&cpu0_0 0 0>,
<&cpu1_0 0 0>,
<&cpu2_0 0 0>;
};
map-devfreq {
cooling-device = <&ga10b 0 0>;
};
};
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

423
nv-platform/tegra234-p3740-0002.dtsi
View File

@@ -4,237 +4,228 @@
#include "nv-soc/tegra234-soc-audio-dai-links.dtsi" #include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX bus@0 {
fragment-t234-p3740-0002@0 { i2c@31c0000 {
target-path = "/"; typec: stusb1600@28 {
__overlay__ { status = "okay";
#endif compatible = "st,stusb1600";
bus@0 { reg = <0x28>;
i2c@31c0000 { vdd-supply = <&p3740_vdd_5v_sys>;
typec: stusb1600@28 { vsys-supply = <&vdd_3v3_sys>;
status = "okay"; interrupt-parent = <&gpio>;
compatible = "st,stusb1600"; interrupts = <TEGRA234_MAIN_GPIO(K, 6) IRQ_TYPE_LEVEL_LOW>;
reg = <0x28>; typec_con: connector {
vdd-supply = <&p3740_vdd_5v_sys>; compatible = "usb-c-connector";
vsys-supply = <&vdd_3v3_sys>; label = "USB-C";
interrupt-parent = <&gpio>; data-role = "dual";
interrupts = <TEGRA234_MAIN_GPIO(K, 6) IRQ_TYPE_LEVEL_LOW>; power-role = "dual";
typec_con: connector { typec-power-opmode = "default";
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
typec-power-opmode = "default";
port { port {
typec_con_ep: endpoint { typec_con_ep: endpoint {
remote-endpoint = <&usb_role_switch0>; remote-endpoint = <&usb_role_switch0>;
};
};
};
};
};
i2c@c250000 {
f75308@4d {
compatible = "fintek,f75308";
reg = <0x4d>;
#address-cells = <1>;
#size-cells = <0>;
fan@0 {
reg = <0x0>;
type = "pwm";
duty = "manual_duty";
5seg = <100 80 60 40 20>;
};
fan@1 {
reg = <0x1>;
type = "pwm";
duty = "manual_duty";
5seg = <100 80 60 40 20>;
};
fan@2 {
reg = <0x2>;
type = "pwm";
duty = "manual_duty";
5seg = <100 80 60 40 20>;
};
fan@3 {
reg = <0x3>;
type = "pwm";
duty = "manual_duty";
5seg = <100 80 60 40 20>;
};
};
};
padctl@3520000 {
ports {
usb2-0 {
port {
usb_role_switch0: endpoint {
remote-endpoint = <&typec_con_ep>;
};
};
}; };
}; };
}; };
}; };
};
i2c@c250000 {
f75308@4d {
compatible = "fintek,f75308";
reg = <0x4d>;
#address-cells = <1>;
#size-cells = <0>;
sound { fan@0 {
compatible = "nvidia,tegra186-audio-graph-card", reg = <0x0>;
"nvidia,tegra186-ape"; type = "pwm";
clocks = <&bpmp TEGRA234_CLK_PLLA>, duty = "manual_duty";
<&bpmp TEGRA234_CLK_PLLA_OUT0>, 5seg = <100 80 60 40 20>;
<&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "pll_a", "plla_out0", "extern1";
assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
nvidia-audio-card,name = "NVIDIA Jetson IGX Orin APE";
nvidia-audio-card,mclk-fs = <256>;
nvidia-audio-card,widgets =
"Headphone", "CVB-RT Headphone Jack",
"Microphone", "CVB-RT Mic Jack",
"Speaker", "CVB-RT Int Spk",
"Microphone", "CVB-RT Int Mic";
nvidia-audio-card,routing =
"CVB-RT Headphone Jack", "CVB-RT HPOL",
"CVB-RT Headphone Jack", "CVB-RT HPOR",
"CVB-RT IN1P", "CVB-RT Mic Jack",
"CVB-RT IN2P", "CVB-RT Mic Jack",
"CVB-RT IN2N", "CVB-RT Mic Jack",
"CVB-RT IN3P", "CVB-RT Mic Jack",
"CVB-RT Int Spk", "CVB-RT SPOLP",
"CVB-RT Int Spk", "CVB-RT SPORP",
"CVB-RT Int Spk", "CVB-RT LOUTL",
"CVB-RT Int Spk", "CVB-RT LOUTR",
"CVB-RT DMIC1", "CVB-RT Int Mic",
"CVB-RT DMIC2", "CVB-RT Int Mic";
/* I2S4 dai node */
nvidia-audio-card,dai-link@79 {
link-name = "rt5640-playback";
codec {
sound-dai = <&rt5640 0>;
prefix = "CVB-RT";
};
}; };
/* I2S6 dai node */ fan@1 {
nvidia-audio-card,dai-link@81 { reg = <0x1>;
bitclock-master; type = "pwm";
frame-master; duty = "manual_duty";
5seg = <100 80 60 40 20>;
};
fan@2 {
reg = <0x2>;
type = "pwm";
duty = "manual_duty";
5seg = <100 80 60 40 20>;
};
fan@3 {
reg = <0x3>;
type = "pwm";
duty = "manual_duty";
5seg = <100 80 60 40 20>;
}; };
}; };
};
eeprom-manager { padctl@3520000 {
bus@0 { ports {
i2c-bus = <&dp_aux_ch2_i2c>; usb2-0 {
eeprom@1 { port {
slave-address = <0x55>; usb_role_switch0: endpoint {
label = "cvb"; remote-endpoint = <&typec_con_ep>;
};
}; };
}; };
}; };
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma { /* Needed for nvgpu comptags */
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x20000000>; /* 512MB */
alignment = <0x0 0x10000>;
linux,cma-default;
status = "okay";
};
};
p3740_vdd_0v95_AO: regulator-vdd-0v95-AO {
compatible = "regulator-fixed";
regulator-name = "vdd-0v95-AO";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
};
p3740_vdd_12v_sys: regulator-vdd-12v-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-12v-sys";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
p3740_vdd_1v05_AO: regulator-vdd-1v05-AO {
compatible = "regulator-fixed";
regulator-name = "vdd-1v05-AO";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
p3740_vdd_1v0_sys: regulator-vdd-1v0-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-1v0-sys";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
p3740_vdd_1v1_sys: regulator-vdd-1v1-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-1v1-sys";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
p3740_vdd_1v8_AO: regulator-vdd-1v8-AO {
compatible = "regulator-fixed";
regulator-name = "vdd-1v8-AO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
p3740_vdd_1v8_sys: regulator-vdd-1v8-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-1v8-sys";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
p3740_vdd_2v5_sys: regulator-vdd-2v5-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-2v5-sys";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
p3740_vdd_2v8_sys: regulator-vdd-2v8-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-2v8-sys";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
p3740_vdd_3v3_AO: regulator-vdd-3v3-AO {
compatible = "regulator-fixed";
regulator-name = "vdd-3v3-AO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
p3740_vdd_3v7_AO: regulator-vdd-3v7-AO {
compatible = "regulator-fixed";
regulator-name = "vdd-3v7-AO";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
p3740_vdd_5v_sys: regulator-vdd-5v-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-5v-sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
sound {
compatible = "nvidia,tegra186-audio-graph-card",
"nvidia,tegra186-ape";
clocks = <&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLA_OUT0>,
<&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "pll_a", "plla_out0", "extern1";
assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
nvidia-audio-card,name = "NVIDIA Jetson IGX Orin APE";
nvidia-audio-card,mclk-fs = <256>;
nvidia-audio-card,widgets =
"Headphone", "CVB-RT Headphone Jack",
"Microphone", "CVB-RT Mic Jack",
"Speaker", "CVB-RT Int Spk",
"Microphone", "CVB-RT Int Mic";
nvidia-audio-card,routing =
"CVB-RT Headphone Jack", "CVB-RT HPOL",
"CVB-RT Headphone Jack", "CVB-RT HPOR",
"CVB-RT IN1P", "CVB-RT Mic Jack",
"CVB-RT IN2P", "CVB-RT Mic Jack",
"CVB-RT IN2N", "CVB-RT Mic Jack",
"CVB-RT IN3P", "CVB-RT Mic Jack",
"CVB-RT Int Spk", "CVB-RT SPOLP",
"CVB-RT Int Spk", "CVB-RT SPORP",
"CVB-RT Int Spk", "CVB-RT LOUTL",
"CVB-RT Int Spk", "CVB-RT LOUTR",
"CVB-RT DMIC1", "CVB-RT Int Mic",
"CVB-RT DMIC2", "CVB-RT Int Mic";
/* I2S4 dai node */
nvidia-audio-card,dai-link@79 {
link-name = "rt5640-playback";
codec {
sound-dai = <&rt5640 0>;
prefix = "CVB-RT";
};
};
/* I2S6 dai node */
nvidia-audio-card,dai-link@81 {
bitclock-master;
frame-master;
};
};
eeprom-manager {
bus@0 {
i2c-bus = <&dp_aux_ch2_i2c>;
eeprom@1 {
slave-address = <0x55>;
label = "cvb";
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma { /* Needed for nvgpu comptags */
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x20000000>; /* 512MB */
alignment = <0x0 0x10000>;
linux,cma-default;
status = "okay";
};
};
p3740_vdd_0v95_AO: regulator-vdd-0v95-AO {
compatible = "regulator-fixed";
regulator-name = "vdd-0v95-AO";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
};
p3740_vdd_12v_sys: regulator-vdd-12v-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-12v-sys";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
p3740_vdd_1v05_AO: regulator-vdd-1v05-AO {
compatible = "regulator-fixed";
regulator-name = "vdd-1v05-AO";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
p3740_vdd_1v0_sys: regulator-vdd-1v0-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-1v0-sys";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
p3740_vdd_1v1_sys: regulator-vdd-1v1-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-1v1-sys";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
p3740_vdd_1v8_AO: regulator-vdd-1v8-AO {
compatible = "regulator-fixed";
regulator-name = "vdd-1v8-AO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
p3740_vdd_1v8_sys: regulator-vdd-1v8-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-1v8-sys";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
p3740_vdd_2v5_sys: regulator-vdd-2v5-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-2v5-sys";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
p3740_vdd_2v8_sys: regulator-vdd-2v8-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-2v8-sys";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
p3740_vdd_3v3_AO: regulator-vdd-3v3-AO {
compatible = "regulator-fixed";
regulator-name = "vdd-3v3-AO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
p3740_vdd_3v7_AO: regulator-vdd-3v7-AO {
compatible = "regulator-fixed";
regulator-name = "vdd-3v7-AO";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
p3740_vdd_5v_sys: regulator-vdd-5v-sys {
compatible = "regulator-fixed";
regulator-name = "vdd-5v-sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
}; };

132
nv-platform/tegra234-p3767-0000.dtsi
View File

@@ -6,78 +6,68 @@
#include <dt-bindings/interrupt/tegra234-irq.h> #include <dt-bindings/interrupt/tegra234-irq.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX bus@0 {
p3767-0000-fragment@0 { mmc@3400000 {
target-path = "/"; no-sdio;
no-mmc;
nvidia,cd-wakeup-capable;
nvidia,boot-detect-delay = <1000>;
cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
};
__overlay__ { gpu@17000000 {
#endif status = "okay";
bus@0 { };
mmc@3400000 { };
no-sdio;
no-mmc; chosen {
nvidia,cd-wakeup-capable; nvidia,tegra-joint_xpu_rail;
nvidia,boot-detect-delay = <1000>; };
cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
}; opp-table-cluster0 {
opp-1510400000 { /* Max CPU freq for Orin Nano */
gpu@17000000 { opp-hz = /bits/ 64 <1510400000>;
status = "okay"; opp-peak-kBps = <3200000>;
}; };
};
opp-1984000000 { /* Max CPU freq for ONX */
chosen { opp-hz = /bits/ 64 <1984000000>;
nvidia,tegra-joint_xpu_rail; opp-peak-kBps = <3200000>;
}; };
};
opp-table-cluster0 {
opp-1510400000 { /* Max CPU freq for Orin Nano */ opp-table-cluster1 {
opp-hz = /bits/ 64 <1510400000>; opp-1510400000 { /* Max CPU freq for Orin Nano */
opp-peak-kBps = <3200000>; opp-hz = /bits/ 64 <1510400000>;
}; opp-peak-kBps = <3200000>;
};
opp-1984000000 { /* Max CPU freq for ONX */
opp-hz = /bits/ 64 <1984000000>; opp-1984000000 { /* Max CPU freq for ONX */
opp-peak-kBps = <3200000>; opp-hz = /bits/ 64 <1984000000>;
}; opp-peak-kBps = <3200000>;
}; };
};
opp-table-cluster1 {
opp-1510400000 { /* Max CPU freq for Orin Nano */ opp-table-cluster2 {
opp-hz = /bits/ 64 <1510400000>; opp-1510400000 { /* Max CPU freq for Orin Nano */
opp-peak-kBps = <3200000>; opp-hz = /bits/ 64 <1510400000>;
}; opp-peak-kBps = <3200000>;
};
opp-1984000000 { /* Max CPU freq for ONX */
opp-hz = /bits/ 64 <1984000000>; opp-1984000000 { /* Max CPU freq for ONX */
opp-peak-kBps = <3200000>; opp-hz = /bits/ 64 <1984000000>;
}; opp-peak-kBps = <3200000>;
}; };
};
opp-table-cluster2 {
opp-1510400000 { /* Max CPU freq for Orin Nano */ reserved-memory {
opp-hz = /bits/ 64 <1510400000>; linux,cma { /* Needed for nvgpu comptags */
opp-peak-kBps = <3200000>; compatible = "shared-dma-pool";
}; reusable;
size = <0x0 0x10000000>; /* 256MB */
opp-1984000000 { /* Max CPU freq for ONX */ alignment = <0x0 0x10000>;
opp-hz = /bits/ 64 <1984000000>; linux,cma-default;
opp-peak-kBps = <3200000>; status = "okay";
};
};
reserved-memory {
linux,cma { /* Needed for nvgpu comptags */
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x10000000>; /* 256MB */
alignment = <0x0 0x10000>;
linux,cma-default;
status = "okay";
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

1
nv-platform/tegra234-p3768-0000+p3767-0000-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "tegra234-p3768-0000+p3767-0000.dts" #include "tegra234-p3768-0000+p3767-0000.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi" #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3768-0000+p3767-0001-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3768-0000+p3767-0001.dts" #include "staging/tegra234-p3768-0000+p3767-0001.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi" #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3768-0000+p3767-0003-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3768-0000+p3767-0003.dts" #include "staging/tegra234-p3768-0000+p3767-0003.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi" #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3768-0000+p3767-0004-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "staging/tegra234-p3768-0000+p3767-0004.dts" #include "staging/tegra234-p3768-0000+p3767-0004.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi" #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

1
nv-platform/tegra234-p3768-0000+p3767-0005-nv.dts
View File

@@ -3,6 +3,5 @@
/dts-v1/; /dts-v1/;
#define REMOVE_FRAGMENT_SYNTAX 1
#include "tegra234-p3768-0000+p3767-0005.dts" #include "tegra234-p3768-0000+p3767-0005.dts"
#include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi" #include "tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi"

875
nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi
View File

@@ -12,451 +12,440 @@
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi" #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX bpmp {
overlay-name = "Tegra234 P3768-0000+P3767-0000 Overlay"; i2c {
vrs@3c {
fragment-t234-p3768-p3767@0 { compatible = "nvidia,vrs-pseq";
target-path = "/"; reg = <0x3c>;
__overlay__ { interrupt-parent = <&pmc>;
#endif /* VRS Wake ID is 24 */
bpmp { interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
i2c { interrupt-controller;
vrs@3c { #interrupt-cells = <2>;
compatible = "nvidia,vrs-pseq";
reg = <0x3c>;
interrupt-parent = <&pmc>;
/* VRS Wake ID is 24 */
interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
};
};
};
bus@0 {
actmon@d230000 {
status = "okay";
};
pinmux@2430000 {
status = "okay";
};
aconnect@2900000 {
ahub@2900800 {
i2s@2901200 {
status = "okay";
};
i2s@2901400 {
status = "okay";
};
dmic@2904000 {
status = "okay";
};
dmic@2904100 {
status = "okay";
};
dmic@2904300 {
status = "okay";
};
dspk@2905000 {
status = "okay";
};
dspk@2905100 {
status = "okay";
};
afc@2907000 {
status = "okay";
};
afc@2907100 {
status = "okay";
};
afc@2907200 {
status = "okay";
};
afc@2907300 {
status = "okay";
};
afc@2907400 {
status = "okay";
};
afc@2907500 {
status = "okay";
};
arad@290e400 {
status = "okay";
};
};
};
/* UARTA, 40 pin header, Pin 8(TX), Pin 10(RX) */
serial@3100000 {
compatible = "nvidia,tegra194-hsuart";
status = "okay";
};
/* UARTE, M2.E connector */
serial@3140000 {
compatible = "nvidia,tegra194-hsuart";
status = "okay";
};
i2c@3180000 {
status = "okay";
};
i2c@31b0000 {
status = "okay";
};
hdr40_i2c1: i2c@c250000 {
status = "okay";
};
/* SPI1, 40pin header, Pin 19(MOSI), Pin 21(MISO), Pin 23(CLK), Pin 24(CS) */
spi@3210000{
status = "okay";
spi@0 {
compatible = "tegra-spidev";
reg = <0x0>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@1 {
compatible = "tegra-spidev";
reg = <0x1>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};
/* SPI3, 40pin header, Pin 37(MOSI), Pin 22(MISO), Pin 13(CLK), Pin 18(CS) */
spi@3230000{
status = "okay";
spi@0 {
compatible = "tegra-spidev";
reg = <0x0>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@1 {
compatible = "tegra-spidev";
reg = <0x1>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};
padctl@3520000 {
ports {
usb2-0 {
port {
typec_p0: endpoint {
remote-endpoint = <&fusb_p0>;
};
};
};
};
};
i2c@c240000 {
status = "okay";
ina32211_1_40: ina3221@40 {
compatible = "ti,ina3221";
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
label = "VDD_IN";
shunt-resistor-micro-ohms = <5000>;
};
channel@1 {
reg = <0x1>;
label = "VDD_CPU_GPU_CV";
shunt-resistor-micro-ohms = <5000>;
};
channel@2 {
reg = <0x2>;
label = "VDD_SOC";
shunt-resistor-micro-ohms = <5000>;
};
};
fusb301@25 {
compatible = "onsemi,fusb301";
reg = <0x25>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA234_MAIN_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
connector@0 {
port@0 {
fusb_p0: endpoint {
remote-endpoint = <&typec_p0>;
};
};
};
};
};
/* C1 - M.2 Key-E */
pcie@14100000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_3>;
phy-names = "p2u-0";
};
/* C4 - M.2 Key-M */
pcie@14160000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
<&p2u_hsio_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
/* C8 - Ethernet */
pcie@140a0000 {
status = "okay";
num-lanes = <2>;
phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
phy-names = "p2u-0", "p2u-1";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
vpcie3v3-supply = <&vdd_3v3_pcie>;
};
/* C7 - M.2 Key-M */
pcie@141e0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
phy-names = "p2u-0", "p2u-1";
};
/* PWM1, 40pin header, pin 15 */
pwm@3280000 {
status = "okay";
};
/* PWM3, FAN */
pwm@32a0000 {
status = "okay";
};
/* PWM5, 40pin header, pin 33 */
pwm@32c0000 {
status = "okay";
};
/* PWM7, 40pin header, pin 32 */
pwm@32e0000 {
status = "okay";
};
serial@31d0000 {
current-speed = <115200>;
};
tachometer@39c0000 {
status = "okay";
upper-threshold = <0xfffff>;
lower-threshold = <0x0>;
};
hsp@3d00000 {
status = "okay";
};
aon@c000000 {
status = "okay";
};
hardware-timestamp@c1e0000 {
status = "okay";
nvidia,num-slices = <3>;
};
mttcan@c310000 {
status = "okay";
};
host1x@13e00000 {
nvdec@15480000 {
status = "okay";
};
nvenc@154c0000 {
status = "okay";
};
tegra_soc_hwpm {
status = "okay";
};
nvdla0@15880000 {
status = "okay";
};
nvdla1@158c0000 {
status = "okay";
};
ofa@15a50000 {
status = "okay";
};
pva0@16000000 {
status = "okay";
pva0_niso1_ctx0 {
status = "okay";
};
pva0_niso1_ctx1 {
status = "okay";
};
pva0_niso1_ctx2 {
status = "okay";
};
pva0_niso1_ctx3 {
status = "okay";
};
pva0_niso1_ctx4 {
status = "okay";
};
pva0_niso1_ctx5 {
status = "okay";
};
pva0_niso1_ctx6 {
status = "okay";
};
pva0_niso1_ctx7 {
status = "okay";
};
};
nvjpg@15380000 {
status = "okay";
};
nvjpg@15540000 {
status = "okay";
};
};
};
cpus {
idle-states {
c7 {
status = "okay";
};
};
};
nvpmodel {
status = "okay"; status = "okay";
}; };
soctherm-oc-event {
status = "okay";
};
thermal-zones {
cpu-thermal {
status = "okay";
};
gpu-thermal {
status = "okay";
};
cv0-thermal {
status = "okay";
};
cv1-thermal {
status = "okay";
};
cv2-thermal {
status = "okay";
};
soc0-thermal {
status = "okay";
};
soc1-thermal {
status = "okay";
};
soc2-thermal {
status = "okay";
};
};
dce@d800000 {
status = "okay";
};
display@13800000 {
status = "okay";
};
tegra-hsp@b950000 {
status = "okay";
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
bus@0 {
actmon@d230000 {
status = "okay";
};
pinmux@2430000 {
status = "okay";
};
aconnect@2900000 {
ahub@2900800 {
i2s@2901200 {
status = "okay";
};
i2s@2901400 {
status = "okay";
};
dmic@2904000 {
status = "okay";
};
dmic@2904100 {
status = "okay";
};
dmic@2904300 {
status = "okay";
};
dspk@2905000 {
status = "okay";
};
dspk@2905100 {
status = "okay";
};
afc@2907000 {
status = "okay";
};
afc@2907100 {
status = "okay";
};
afc@2907200 {
status = "okay";
};
afc@2907300 {
status = "okay";
};
afc@2907400 {
status = "okay";
};
afc@2907500 {
status = "okay";
};
arad@290e400 {
status = "okay";
};
};
};
/* UARTA, 40 pin header, Pin 8(TX), Pin 10(RX) */
serial@3100000 {
compatible = "nvidia,tegra194-hsuart";
status = "okay";
};
/* UARTE, M2.E connector */
serial@3140000 {
compatible = "nvidia,tegra194-hsuart";
status = "okay";
};
i2c@3180000 {
status = "okay";
};
i2c@31b0000 {
status = "okay";
};
hdr40_i2c1: i2c@c250000 {
status = "okay";
};
/* SPI1, 40pin header, Pin 19(MOSI), Pin 21(MISO), Pin 23(CLK), Pin 24(CS) */
spi@3210000{
status = "okay";
spi@0 {
compatible = "tegra-spidev";
reg = <0x0>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@1 {
compatible = "tegra-spidev";
reg = <0x1>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};
/* SPI3, 40pin header, Pin 37(MOSI), Pin 22(MISO), Pin 13(CLK), Pin 18(CS) */
spi@3230000{
status = "okay";
spi@0 {
compatible = "tegra-spidev";
reg = <0x0>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
spi@1 {
compatible = "tegra-spidev";
reg = <0x1>;
spi-max-frequency = <50000000>;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};
padctl@3520000 {
ports {
usb2-0 {
port {
typec_p0: endpoint {
remote-endpoint = <&fusb_p0>;
};
};
};
};
};
i2c@c240000 {
status = "okay";
ina32211_1_40: ina3221@40 {
compatible = "ti,ina3221";
reg = <0x40>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
channel@0 {
reg = <0x0>;
label = "VDD_IN";
shunt-resistor-micro-ohms = <5000>;
};
channel@1 {
reg = <0x1>;
label = "VDD_CPU_GPU_CV";
shunt-resistor-micro-ohms = <5000>;
};
channel@2 {
reg = <0x2>;
label = "VDD_SOC";
shunt-resistor-micro-ohms = <5000>;
};
};
fusb301@25 {
compatible = "onsemi,fusb301";
reg = <0x25>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA234_MAIN_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
connector@0 {
port@0 {
fusb_p0: endpoint {
remote-endpoint = <&typec_p0>;
};
};
};
};
};
/* C1 - M.2 Key-E */
pcie@14100000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_3>;
phy-names = "p2u-0";
};
/* C4 - M.2 Key-M */
pcie@14160000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
<&p2u_hsio_7>;
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
/* C8 - Ethernet */
pcie@140a0000 {
status = "okay";
num-lanes = <2>;
phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
phy-names = "p2u-0", "p2u-1";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
vpcie3v3-supply = <&vdd_3v3_pcie>;
};
/* C7 - M.2 Key-M */
pcie@141e0000 {
status = "okay";
vddio-pex-ctl-supply = <&vdd_1v8_ao>;
phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
phy-names = "p2u-0", "p2u-1";
};
/* PWM1, 40pin header, pin 15 */
pwm@3280000 {
status = "okay";
};
/* PWM3, FAN */
pwm@32a0000 {
status = "okay";
};
/* PWM5, 40pin header, pin 33 */
pwm@32c0000 {
status = "okay";
};
/* PWM7, 40pin header, pin 32 */
pwm@32e0000 {
status = "okay";
};
serial@31d0000 {
current-speed = <115200>;
};
tachometer@39c0000 {
status = "okay";
upper-threshold = <0xfffff>;
lower-threshold = <0x0>;
};
hsp@3d00000 {
status = "okay";
};
aon@c000000 {
status = "okay";
};
hardware-timestamp@c1e0000 {
status = "okay";
nvidia,num-slices = <3>;
};
mttcan@c310000 {
status = "okay";
};
host1x@13e00000 {
nvdec@15480000 {
status = "okay";
};
nvenc@154c0000 {
status = "okay";
};
tegra_soc_hwpm {
status = "okay";
};
nvdla0@15880000 {
status = "okay";
};
nvdla1@158c0000 {
status = "okay";
};
ofa@15a50000 {
status = "okay";
};
pva0@16000000 {
status = "okay";
pva0_niso1_ctx0 {
status = "okay";
};
pva0_niso1_ctx1 {
status = "okay";
};
pva0_niso1_ctx2 {
status = "okay";
};
pva0_niso1_ctx3 {
status = "okay";
};
pva0_niso1_ctx4 {
status = "okay";
};
pva0_niso1_ctx5 {
status = "okay";
};
pva0_niso1_ctx6 {
status = "okay";
};
pva0_niso1_ctx7 {
status = "okay";
};
};
nvjpg@15380000 {
status = "okay";
};
nvjpg@15540000 {
status = "okay";
};
};
};
cpus {
idle-states {
c7 {
status = "okay";
};
};
};
nvpmodel {
status = "okay";
};
soctherm-oc-event {
status = "okay";
};
thermal-zones {
cpu-thermal {
status = "okay";
};
gpu-thermal {
status = "okay";
};
cv0-thermal {
status = "okay";
};
cv1-thermal {
status = "okay";
};
cv2-thermal {
status = "okay";
};
soc0-thermal {
status = "okay";
};
soc1-thermal {
status = "okay";
};
soc2-thermal {
status = "okay";
};
};
dce@d800000 {
status = "okay";
};
display@13800000 {
status = "okay";
};
tegra-hsp@b950000 {
status = "okay";
};
}; };

55
nv-platform/tegra234-p3768-0000.dtsi
View File

@@ -2,44 +2,35 @@
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX bus@0 {
fragment-t234-p3768-0000@0 {
target-path = "/";
__overlay__ {
#endif
bus@0 {
aconnect@2900000 { aconnect@2900000 {
ahub@2900800 { ahub@2900800 {
i2s@2901100 { i2s@2901100 {
ports { ports {
port@1 { port@1 {
hdr40_snd_i2s_dap_ep: endpoint { hdr40_snd_i2s_dap_ep: endpoint {
};
};
}; };
}; };
}; };
}; };
}; };
tegra_sound_graph: tegra_sound: sound {
compatible = "nvidia,tegra186-audio-graph-card",
"nvidia,tegra186-ape";
clocks = <&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLA_OUT0>,
<&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "pll_a", "plla_out0", "extern1";
assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
nvidia-audio-card,name = "NVIDIA Jetson Orin NX APE";
hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { };
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
};
tegra_sound_graph: tegra_sound: sound {
compatible = "nvidia,tegra186-audio-graph-card",
"nvidia,tegra186-ape";
clocks = <&bpmp TEGRA234_CLK_PLLA>,
<&bpmp TEGRA234_CLK_PLLA_OUT0>,
<&bpmp TEGRA234_CLK_AUD_MCLK>;
clock-names = "pll_a", "plla_out0", "extern1";
assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
nvidia-audio-card,name = "NVIDIA Jetson Orin NX APE";
hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { };
}; };
#endif
}; };

1472
nv-soc/tegra234-base-overlay.dtsi
View File

File diff suppressed because it is too large Load Diff

4533
nv-soc/tegra234-soc-audio-dai-links.dtsi
View File

File diff suppressed because it is too large Load Diff

479
nv-soc/tegra234-soc-camera.dtsi
View File

@@ -12,262 +12,253 @@
#include <dt-bindings/memory/tegra234-mc.h> #include <dt-bindings/memory/tegra234-mc.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX aliases { /* RCE is the Camera RTCPU */
fragment-camera@0 { tegra-camera-rtcpu = "/rtcpu@bc00000";
target-path = "/"; };
__overlay__ {
#endif
aliases { /* RCE is the Camera RTCPU */
tegra-camera-rtcpu = "/rtcpu@bc00000";
};
bus@0 { bus@0 {
host1x@13e00000 { host1x@13e00000 {
vi0: vi0@15c00000 { vi0: vi0@15c00000 {
compatible = "nvidia,tegra234-vi"; compatible = "nvidia,tegra234-vi";
clocks = <&bpmp TEGRA234_CLK_VI>; clocks = <&bpmp TEGRA234_CLK_VI>;
clock-names = "vi"; clock-names = "vi";
nvidia,vi-falcon-device = <&vi0_thi>; nvidia,vi-falcon-device = <&vi0_thi>;
resets = <&bpmp TEGRA234_RESET_VI>; resets = <&bpmp TEGRA234_RESET_VI>;
reset-names = "vi0"; reset-names = "vi0";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI>; iommus = <&smmu_iso TEGRA234_SID_ISO_VI>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIW &emc>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIW &emc>;
interconnect-names = "write"; interconnect-names = "write";
non-coherent; non-coherent;
status = "okay";
};
vi0_thi: vi0-thi@15f00000 {
compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI>;
reset-names = "vi0_thi";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2FALR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_VI2FALW &emc>;
interconnect-names = "dma-mem", "write";
status = "okay";
};
vi1: vi1@14c00000 {
compatible = "nvidia,tegra234-vi";
clocks = <&bpmp TEGRA234_CLK_VI>;
clock-names = "vi";
nvidia,vi-falcon-device = <&vi1_thi>;
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI2>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2W &emc>;
interconnect-names = "write";
non-coherent;
status = "okay";
};
vi1_thi: vi1-thi@14f00000 {
compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1_thi";
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIFALR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_VIFALW &emc>;
interconnect-names = "dma-mem", "write";
status = "okay";
};
isp: isp@14800000 {
compatible = "nvidia,tegra194-isp";
reg = <0x0 0x14800000 0x0 0x00010000>;
resets = <&bpmp TEGRA234_RESET_ISP>;
reset-names = "isp";
clocks = <&bpmp TEGRA234_CLK_ISP>;
clock-names = "isp";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_ISPA>;
nvidia,isp-falcon-device = <&isp_thi>;
iommus = <&smmu_niso1 TEGRA234_SID_ISP>;
dma-coherent;
status = "okay";
};
isp_thi: isp-thi@14b00000 {
compatible = "nvidia,tegra194-isp-thi";
resets = <&bpmp TEGRA234_RESET_ISP>;
status = "okay";
};
nvcsi: nvcsi@15a00000 {
compatible = "nvidia,tegra194-nvcsi";
resets = <&bpmp TEGRA234_RESET_NVCSI>;
reset-names = "nvcsi";
clocks = <&bpmp TEGRA234_CLK_NVCSI>;
clock-names = "nvcsi";
status = "okay";
};
};
};
tegra_rce: rtcpu@bc00000 {
compatible = "nvidia,tegra194-rce";
nvidia,cpu-name = "rce";
reg = <0 0xbc00000 0 0x1000>, /* RCE EVP (RCE_ATCM_EVP) */
<0 0xb9f0000 0 0x40000>, /* RCE PM */
<0 0xb840000 0 0x10000>,
<0 0xb850000 0 0x10000>;
reg-names = "rce-evp", "rce-pm",
"ast-cpu", "ast-dma";
clocks =
<&bpmp TEGRA234_CLK_RCE_CPU_NIC>,
<&bpmp TEGRA234_CLK_RCE_NIC>,
<&bpmp TEGRA234_CLK_RCE_CPU>;
clock-names = "rce-cpu-nic", "rce-nic", "rce-cpu";
nvidia,clock-rates =
<115200000 601600000>,
<115200000 601600000>,
<115200000 601600000>;
resets = <&bpmp TEGRA234_RESET_RCE_ALL>;
reset-names = "rce-all";
interrupts = <GIC_SPI TEGRA234_IRQ_RCE_WDT_REMOTE IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt-remote";
iommus = <&smmu_niso0 TEGRA234_SID_RCE>;
memory-region = <&rce_resv>;
dma-coherent;
/* Memory bandwidth in kB/s during boot */
nvidia,test-bw = <2400000>;
nvidia,trace = <&rtcpu_trace 4 0x70100000 0x100000>;
nvidia,ivc-channels = <&camera_ivc_channels 2 0x90000000 0x10000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_RCER &emc>,
<&mc TEGRA234_MEMORY_CLIENT_RCEW &emc>;
interconnect-names = "dma-mem", "write";
nvidia,autosuspend-delay-ms = <5000>;
status = "okay"; status = "okay";
hsp-vm1 {
compatible = "nvidia,tegra-camrtc-hsp-vm";
mboxes =
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(0)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(1)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 0>;
mbox-names = "vm-tx", "vm-rx", "vm-ss";
status = "okay";
};
hsp-vm2 {
compatible = "nvidia,tegra-camrtc-hsp-vm";
mboxes =
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(2)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(3)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 1>;
mbox-names = "vm-tx", "vm-rx", "vm-ss";
status = "disabled";
};
}; };
camera_ivc_channels: camera-ivc-channels { vi0_thi: vi0-thi@15f00000 {
echo@0 { compatible = "nvidia,tegra234-vi-thi";
compatible = "nvidia,tegra186-camera-ivc-protocol-echo"; resets = <&bpmp TEGRA234_RESET_VI>;
nvidia,service = "echo"; reset-names = "vi0_thi";
nvidia,version = <0>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2FALR &emc>,
nvidia,group = <1>; <&mc TEGRA234_MEMORY_CLIENT_VI2FALW &emc>;
nvidia,frame-count = <16>; interconnect-names = "dma-mem", "write";
nvidia,frame-size = <64>; status = "okay";
};
dbg@1 {
/* This is raw channel exposed as device */
compatible = "nvidia,tegra186-camera-ivc-protocol-dbg";
nvidia,service = "debug";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <448>;
};
dbg@2 {
/* This is exposed in debugfs */
compatible = "nvidia,tegra186-camera-ivc-protocol-debug";
nvidia,service = "debug";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <8192>;
nvidia,ivc-timeout = <50>;
nvidia,test-timeout = <5000>;
nvidia,mem-map = <&tegra_rce &vi0 &isp &vi1>;
/* Memory bandwidth in kB/s during tests */
nvidia,test-bw = <2400000>;
};
ivccontrol@3 {
compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control";
nvidia,service = "capture-control";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <64>;
nvidia,frame-size = <320>;
};
ivccapture@4 {
compatible = "nvidia,tegra186-camera-ivc-protocol-capture";
nvidia,service = "capture";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <512>;
nvidia,frame-size = <64>;
};
diag@5 {
compatible = "nvidia,tegra186-camera-diagnostics";
nvidia,service = "diag";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <64>;
};
}; };
rtcpu_trace: tegra-rtcpu-trace { vi1: vi1@14c00000 {
nvidia,enable-printk; compatible = "nvidia,tegra234-vi";
nvidia,interval-ms = <50>; clocks = <&bpmp TEGRA234_CLK_VI>;
nvidia,log-prefix = "[RCE]"; clock-names = "vi";
nvidia,vi-falcon-device = <&vi1_thi>;
resets = <&bpmp TEGRA234_RESET_VI2>;
reset-names = "vi1";
iommus = <&smmu_iso TEGRA234_SID_ISO_VI2>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_VI2W &emc>;
interconnect-names = "write";
non-coherent;
status = "okay";
}; };
capture_vi: tegra-capture-vi { vi1_thi: vi1-thi@14f00000 {
compatible = "nvidia,tegra-camrtc-capture-vi"; compatible = "nvidia,tegra234-vi-thi";
resets = <&bpmp TEGRA234_RESET_VI2>;
nvidia,vi-devices = <&vi0 &vi1>; reset-names = "vi1_thi";
nvidia,vi-mapping-size = <6>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_VIFALR &emc>,
nvidia,vi-mapping = <&mc TEGRA234_MEMORY_CLIENT_VIFALW &emc>;
<0 0>, interconnect-names = "dma-mem", "write";
<1 0>, status = "okay";
<2 1>,
<3 1>,
<4 0>,
<5 1>;
nvidia,vi-mapping-names = "csi-stream-id", "vi-unit-id";
nvidia,vi-max-channels = <72>;
}; };
reserved-memory { isp: isp@14800000 {
rce_resv: rce-reservation { compatible = "nvidia,tegra194-isp";
iommu-addresses = <&tegra_rce 0x0 0x00000000 0x00000000 0xA0000000>, reg = <0x0 0x14800000 0x0 0x00010000>;
<&tegra_rce 0x0 0xC0000000 0xffffffff 0x3fffffff>;
};
camdbg_reserved: camdbg_carveout { resets = <&bpmp TEGRA234_RESET_ISP>;
compatible = "nvidia,camdbg_carveout"; reset-names = "isp";
size = <0 0x3200000>; clocks = <&bpmp TEGRA234_CLK_ISP>;
alignment = <0 0x100000>; clock-names = "isp";
alloc-ranges = <0x1 0 0x1 0>; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_ISPA>;
status = "disabled"; nvidia,isp-falcon-device = <&isp_thi>;
};
iommus = <&smmu_niso1 TEGRA234_SID_ISP>;
dma-coherent;
status = "okay";
};
isp_thi: isp-thi@14b00000 {
compatible = "nvidia,tegra194-isp-thi";
resets = <&bpmp TEGRA234_RESET_ISP>;
status = "okay";
};
nvcsi: nvcsi@15a00000 {
compatible = "nvidia,tegra194-nvcsi";
resets = <&bpmp TEGRA234_RESET_NVCSI>;
reset-names = "nvcsi";
clocks = <&bpmp TEGRA234_CLK_NVCSI>;
clock-names = "nvcsi";
status = "okay";
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
tegra_rce: rtcpu@bc00000 {
compatible = "nvidia,tegra194-rce";
nvidia,cpu-name = "rce";
reg = <0 0xbc00000 0 0x1000>, /* RCE EVP (RCE_ATCM_EVP) */
<0 0xb9f0000 0 0x40000>, /* RCE PM */
<0 0xb840000 0 0x10000>,
<0 0xb850000 0 0x10000>;
reg-names = "rce-evp", "rce-pm",
"ast-cpu", "ast-dma";
clocks =
<&bpmp TEGRA234_CLK_RCE_CPU_NIC>,
<&bpmp TEGRA234_CLK_RCE_NIC>,
<&bpmp TEGRA234_CLK_RCE_CPU>;
clock-names = "rce-cpu-nic", "rce-nic", "rce-cpu";
nvidia,clock-rates =
<115200000 601600000>,
<115200000 601600000>,
<115200000 601600000>;
resets = <&bpmp TEGRA234_RESET_RCE_ALL>;
reset-names = "rce-all";
interrupts = <GIC_SPI TEGRA234_IRQ_RCE_WDT_REMOTE IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt-remote";
iommus = <&smmu_niso0 TEGRA234_SID_RCE>;
memory-region = <&rce_resv>;
dma-coherent;
/* Memory bandwidth in kB/s during boot */
nvidia,test-bw = <2400000>;
nvidia,trace = <&rtcpu_trace 4 0x70100000 0x100000>;
nvidia,ivc-channels = <&camera_ivc_channels 2 0x90000000 0x10000>;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_RCER &emc>,
<&mc TEGRA234_MEMORY_CLIENT_RCEW &emc>;
interconnect-names = "dma-mem", "write";
nvidia,autosuspend-delay-ms = <5000>;
status = "okay";
hsp-vm1 {
compatible = "nvidia,tegra-camrtc-hsp-vm";
mboxes =
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(0)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(1)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 0>;
mbox-names = "vm-tx", "vm-rx", "vm-ss";
status = "okay";
};
hsp-vm2 {
compatible = "nvidia,tegra-camrtc-hsp-vm";
mboxes =
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(2)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(3)>,
<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 1>;
mbox-names = "vm-tx", "vm-rx", "vm-ss";
status = "disabled";
};
};
camera_ivc_channels: camera-ivc-channels {
echo@0 {
compatible = "nvidia,tegra186-camera-ivc-protocol-echo";
nvidia,service = "echo";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <16>;
nvidia,frame-size = <64>;
};
dbg@1 {
/* This is raw channel exposed as device */
compatible = "nvidia,tegra186-camera-ivc-protocol-dbg";
nvidia,service = "debug";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <448>;
};
dbg@2 {
/* This is exposed in debugfs */
compatible = "nvidia,tegra186-camera-ivc-protocol-debug";
nvidia,service = "debug";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <8192>;
nvidia,ivc-timeout = <50>;
nvidia,test-timeout = <5000>;
nvidia,mem-map = <&tegra_rce &vi0 &isp &vi1>;
/* Memory bandwidth in kB/s during tests */
nvidia,test-bw = <2400000>;
};
ivccontrol@3 {
compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control";
nvidia,service = "capture-control";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <64>;
nvidia,frame-size = <320>;
};
ivccapture@4 {
compatible = "nvidia,tegra186-camera-ivc-protocol-capture";
nvidia,service = "capture";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <512>;
nvidia,frame-size = <64>;
};
diag@5 {
compatible = "nvidia,tegra186-camera-diagnostics";
nvidia,service = "diag";
nvidia,version = <0>;
nvidia,group = <1>;
nvidia,frame-count = <1>;
nvidia,frame-size = <64>;
};
};
rtcpu_trace: tegra-rtcpu-trace {
nvidia,enable-printk;
nvidia,interval-ms = <50>;
nvidia,log-prefix = "[RCE]";
};
capture_vi: tegra-capture-vi {
compatible = "nvidia,tegra-camrtc-capture-vi";
nvidia,vi-devices = <&vi0 &vi1>;
nvidia,vi-mapping-size = <6>;
nvidia,vi-mapping =
<0 0>,
<1 0>,
<2 1>,
<3 1>,
<4 0>,
<5 1>;
nvidia,vi-mapping-names = "csi-stream-id", "vi-unit-id";
nvidia,vi-max-channels = <72>;
};
reserved-memory {
rce_resv: rce-reservation {
iommu-addresses = <&tegra_rce 0x0 0x00000000 0x00000000 0xA0000000>,
<&tegra_rce 0x0 0xC0000000 0xffffffff 0x3fffffff>;
};
camdbg_reserved: camdbg_carveout {
compatible = "nvidia,camdbg_carveout";
size = <0 0x3200000>;
alignment = <0 0x100000>;
alloc-ranges = <0x1 0 0x1 0>;
status = "disabled";
};
};
}; };

377
nv-soc/tegra234-soc-display-overlay.dtsi
View File

@@ -4,201 +4,192 @@
#include <dt-bindings/power/tegra234-powergate.h> #include <dt-bindings/power/tegra234-powergate.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX reserved-memory {
fragment-t234-display@0 { #address-cells = <2>;
target-path = "/"; #size-cells = <2>;
__overlay__ { ranges;
#endif
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
fb0_reserved: framebuffer@0,0 { fb0_reserved: framebuffer@0,0 {
compatible = "framebuffer"; compatible = "framebuffer";
reg = <0x00 0x00 0x00 0x00>; reg = <0x00 0x00 0x00 0x00>;
iommu-addresses = <&display 0x0 0x0 0x0 0x0>; iommu-addresses = <&display 0x0 0x0 0x0 0x0>;
no-map; no-map;
status = "disabled"; status = "disabled";
};
};
dce@d800000 {
compatible = "nvidia,tegra234-dce";
reg = <0x0 0x0d800000 0x0 0x00800000>;
interrupts =
<0 376 0x4>,
<0 377 0x4>;
interrupt-names = "wdt-remote",
"dce-sm0";
iommus = <&smmu_niso0 TEGRA234_SID_DCE>;
status = "disabled";
};
display: display@13800000 {
compatible = "nvidia,tegra234-display";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
nvidia,num-dpaux-instance = <1>;
reg-names = "nvdisplay", "dpaux0", "hdacodec", "mipical";
reg = <0x0 0x13800000 0x0 0xEFFFF /* nvdisplay */
0x0 0x155C0000 0x0 0xFFFF /* dpaux0 */
0x0 0x0242c000 0x0 0x1000 /* hdacodec */
0x0 0x03990000 0x0 0x10000>; /* mipical */
interrupt-names = "nvdisplay", "dpaux0", "hdacodec";
interrupts = <0 416 4
0 419 4
0 61 4>;
nvidia,bpmp = <&bpmp>;
clocks = <&bpmp TEGRA234_CLK_HUB>,
<&bpmp TEGRA234_CLK_DISP>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P1>,
<&bpmp TEGRA234_CLK_DPAUX>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_DSIPLL_VCO>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTPN>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_VCO>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTB>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV10>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV25>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV27PN>,
<&bpmp TEGRA234_CLK_SPPLL1_VCO>,
<&bpmp TEGRA234_CLK_SPPLL1_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL1_DIV27PN>,
<&bpmp TEGRA234_CLK_VPLL0_REF>,
<&bpmp TEGRA234_CLK_VPLL0>,
<&bpmp TEGRA234_CLK_VPLL1>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0_REF>,
<&bpmp TEGRA234_CLK_RG0>,
<&bpmp TEGRA234_CLK_RG1>,
<&bpmp TEGRA234_CLK_DISPPLL>,
<&bpmp TEGRA234_CLK_DISPHUBPLL>,
<&bpmp TEGRA234_CLK_DSI_LP>,
<&bpmp TEGRA234_CLK_DSI_CORE>,
<&bpmp TEGRA234_CLK_DSI_PIXEL>,
<&bpmp TEGRA234_CLK_PRE_SOR0>,
<&bpmp TEGRA234_CLK_PRE_SOR1>,
<&bpmp TEGRA234_CLK_DP_LINK_REF>,
<&bpmp TEGRA234_CLK_SOR_LINKA_INPUT>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
<&bpmp TEGRA234_CLK_RG0_M>,
<&bpmp TEGRA234_CLK_RG1_M>,
<&bpmp TEGRA234_CLK_SOR0_M>,
<&bpmp TEGRA234_CLK_SOR1_M>,
<&bpmp TEGRA234_CLK_PLLHUB>,
<&bpmp TEGRA234_CLK_SOR0>,
<&bpmp TEGRA234_CLK_SOR1>,
<&bpmp TEGRA234_CLK_SOR_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SF0>,
<&bpmp TEGRA234_CLK_SF0>,
<&bpmp TEGRA234_CLK_SF1>,
<&bpmp TEGRA234_CLK_DSI_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SOR0_REF>,
<&bpmp TEGRA234_CLK_PRE_SOR1_REF>,
<&bpmp TEGRA234_CLK_SOR0_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR1_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR0_REF>,
<&bpmp TEGRA234_CLK_SOR1_REF>,
<&bpmp TEGRA234_CLK_OSC>,
<&bpmp TEGRA234_CLK_DSC>,
<&bpmp TEGRA234_CLK_MAUD>,
<&bpmp TEGRA234_CLK_AZA_2XBIT>,
<&bpmp TEGRA234_CLK_AZA_BIT>,
<&bpmp TEGRA234_CLK_MIPI_CAL>,
<&bpmp TEGRA234_CLK_UART_FST_MIPI_CAL>,
<&bpmp TEGRA234_CLK_SOR0_DIV>;
clock-names = "nvdisplayhub_clk",
"nvdisplay_disp_clk",
"nvdisplay_p0_clk",
"nvdisplay_p1_clk",
"dpaux0_clk",
"fuse_clk",
"dsipll_vco_clk",
"dsipll_clkoutpn_clk",
"dsipll_clkouta_clk",
"sppll0_vco_clk",
"sppll0_clkoutpn_clk",
"sppll0_clkouta_clk",
"sppll0_clkoutb_clk",
"sppll0_div10_clk",
"sppll0_div25_clk",
"sppll0_div27_clk",
"sppll1_vco_clk",
"sppll1_clkoutpn_clk",
"sppll1_div27_clk",
"vpll0_ref_clk",
"vpll0_clk",
"vpll1_clk",
"nvdisplay_p0_ref_clk",
"rg0_clk",
"rg1_clk",
"disppll_clk",
"disphubpll_clk",
"dsi_lp_clk",
"dsi_core_clk",
"dsi_pixel_clk",
"pre_sor0_clk",
"pre_sor1_clk",
"dp_link_ref_clk",
"sor_linka_input_clk",
"sor_linka_afifo_clk",
"sor_linka_afifo_m_clk",
"rg0_m_clk",
"rg1_m_clk",
"sor0_m_clk",
"sor1_m_clk",
"pllhub_clk",
"sor0_clk",
"sor1_clk",
"sor_pad_input_clk",
"pre_sf0_clk",
"sf0_clk",
"sf1_clk",
"dsi_pad_input_clk",
"pre_sor0_ref_clk",
"pre_sor1_ref_clk",
"sor0_ref_pll_clk",
"sor1_ref_pll_clk",
"sor0_ref_clk",
"sor1_ref_clk",
"osc_clk",
"dsc_clk",
"maud_clk",
"aza_2xbit_clk",
"aza_bit_clk",
"mipi_cal_clk",
"uart_fst_mipi_cal_clk",
"sor0_div_clk";
resets = <&bpmp TEGRA234_RESET_NVDISPLAY>,
<&bpmp TEGRA234_RESET_DPAUX>,
<&bpmp TEGRA234_RESET_DSI_CORE>,
<&bpmp TEGRA234_RESET_MIPI_CAL>;
reset-names = "nvdisplay_reset",
"dpaux0_reset",
"dsi_core_reset",
"mipi_cal_reset";
status = "disabled";
memory-region = <&fb0_reserved>;
nvidia,disp-sw-soc-chip-id = <0x2350>;
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
#endif
iommus = <&smmu_iso TEGRA234_SID_ISO_NVDISPLAY>;
non-coherent;
nvdisplay-niso {
compatible = "nvidia,tegra234-display-niso";
iommus = <&smmu_niso0 TEGRA234_SID_NVDISPLAY>;
dma-coherent;
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
dce@d800000 {
compatible = "nvidia,tegra234-dce";
reg = <0x0 0x0d800000 0x0 0x00800000>;
interrupts =
<0 376 0x4>,
<0 377 0x4>;
interrupt-names = "wdt-remote",
"dce-sm0";
iommus = <&smmu_niso0 TEGRA234_SID_DCE>;
status = "disabled";
};
display: display@13800000 {
compatible = "nvidia,tegra234-display";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
nvidia,num-dpaux-instance = <1>;
reg-names = "nvdisplay", "dpaux0", "hdacodec", "mipical";
reg = <0x0 0x13800000 0x0 0xEFFFF /* nvdisplay */
0x0 0x155C0000 0x0 0xFFFF /* dpaux0 */
0x0 0x0242c000 0x0 0x1000 /* hdacodec */
0x0 0x03990000 0x0 0x10000>; /* mipical */
interrupt-names = "nvdisplay", "dpaux0", "hdacodec";
interrupts = <0 416 4
0 419 4
0 61 4>;
nvidia,bpmp = <&bpmp>;
clocks = <&bpmp TEGRA234_CLK_HUB>,
<&bpmp TEGRA234_CLK_DISP>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P1>,
<&bpmp TEGRA234_CLK_DPAUX>,
<&bpmp TEGRA234_CLK_FUSE>,
<&bpmp TEGRA234_CLK_DSIPLL_VCO>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTPN>,
<&bpmp TEGRA234_CLK_DSIPLL_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_VCO>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTA>,
<&bpmp TEGRA234_CLK_SPPLL0_CLKOUTB>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV10>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV25>,
<&bpmp TEGRA234_CLK_SPPLL0_DIV27PN>,
<&bpmp TEGRA234_CLK_SPPLL1_VCO>,
<&bpmp TEGRA234_CLK_SPPLL1_CLKOUTPN>,
<&bpmp TEGRA234_CLK_SPPLL1_DIV27PN>,
<&bpmp TEGRA234_CLK_VPLL0_REF>,
<&bpmp TEGRA234_CLK_VPLL0>,
<&bpmp TEGRA234_CLK_VPLL1>,
<&bpmp TEGRA234_CLK_NVDISPLAY_P0_REF>,
<&bpmp TEGRA234_CLK_RG0>,
<&bpmp TEGRA234_CLK_RG1>,
<&bpmp TEGRA234_CLK_DISPPLL>,
<&bpmp TEGRA234_CLK_DISPHUBPLL>,
<&bpmp TEGRA234_CLK_DSI_LP>,
<&bpmp TEGRA234_CLK_DSI_CORE>,
<&bpmp TEGRA234_CLK_DSI_PIXEL>,
<&bpmp TEGRA234_CLK_PRE_SOR0>,
<&bpmp TEGRA234_CLK_PRE_SOR1>,
<&bpmp TEGRA234_CLK_DP_LINK_REF>,
<&bpmp TEGRA234_CLK_SOR_LINKA_INPUT>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO>,
<&bpmp TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
<&bpmp TEGRA234_CLK_RG0_M>,
<&bpmp TEGRA234_CLK_RG1_M>,
<&bpmp TEGRA234_CLK_SOR0_M>,
<&bpmp TEGRA234_CLK_SOR1_M>,
<&bpmp TEGRA234_CLK_PLLHUB>,
<&bpmp TEGRA234_CLK_SOR0>,
<&bpmp TEGRA234_CLK_SOR1>,
<&bpmp TEGRA234_CLK_SOR_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SF0>,
<&bpmp TEGRA234_CLK_SF0>,
<&bpmp TEGRA234_CLK_SF1>,
<&bpmp TEGRA234_CLK_DSI_PAD_INPUT>,
<&bpmp TEGRA234_CLK_PRE_SOR0_REF>,
<&bpmp TEGRA234_CLK_PRE_SOR1_REF>,
<&bpmp TEGRA234_CLK_SOR0_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR1_PLL_REF>,
<&bpmp TEGRA234_CLK_SOR0_REF>,
<&bpmp TEGRA234_CLK_SOR1_REF>,
<&bpmp TEGRA234_CLK_OSC>,
<&bpmp TEGRA234_CLK_DSC>,
<&bpmp TEGRA234_CLK_MAUD>,
<&bpmp TEGRA234_CLK_AZA_2XBIT>,
<&bpmp TEGRA234_CLK_AZA_BIT>,
<&bpmp TEGRA234_CLK_MIPI_CAL>,
<&bpmp TEGRA234_CLK_UART_FST_MIPI_CAL>,
<&bpmp TEGRA234_CLK_SOR0_DIV>;
clock-names = "nvdisplayhub_clk",
"nvdisplay_disp_clk",
"nvdisplay_p0_clk",
"nvdisplay_p1_clk",
"dpaux0_clk",
"fuse_clk",
"dsipll_vco_clk",
"dsipll_clkoutpn_clk",
"dsipll_clkouta_clk",
"sppll0_vco_clk",
"sppll0_clkoutpn_clk",
"sppll0_clkouta_clk",
"sppll0_clkoutb_clk",
"sppll0_div10_clk",
"sppll0_div25_clk",
"sppll0_div27_clk",
"sppll1_vco_clk",
"sppll1_clkoutpn_clk",
"sppll1_div27_clk",
"vpll0_ref_clk",
"vpll0_clk",
"vpll1_clk",
"nvdisplay_p0_ref_clk",
"rg0_clk",
"rg1_clk",
"disppll_clk",
"disphubpll_clk",
"dsi_lp_clk",
"dsi_core_clk",
"dsi_pixel_clk",
"pre_sor0_clk",
"pre_sor1_clk",
"dp_link_ref_clk",
"sor_linka_input_clk",
"sor_linka_afifo_clk",
"sor_linka_afifo_m_clk",
"rg0_m_clk",
"rg1_m_clk",
"sor0_m_clk",
"sor1_m_clk",
"pllhub_clk",
"sor0_clk",
"sor1_clk",
"sor_pad_input_clk",
"pre_sf0_clk",
"sf0_clk",
"sf1_clk",
"dsi_pad_input_clk",
"pre_sor0_ref_clk",
"pre_sor1_ref_clk",
"sor0_ref_pll_clk",
"sor1_ref_pll_clk",
"sor0_ref_clk",
"sor1_ref_clk",
"osc_clk",
"dsc_clk",
"maud_clk",
"aza_2xbit_clk",
"aza_bit_clk",
"mipi_cal_clk",
"uart_fst_mipi_cal_clk",
"sor0_div_clk";
resets = <&bpmp TEGRA234_RESET_NVDISPLAY>,
<&bpmp TEGRA234_RESET_DPAUX>,
<&bpmp TEGRA234_RESET_DSI_CORE>,
<&bpmp TEGRA234_RESET_MIPI_CAL>;
reset-names = "nvdisplay_reset",
"dpaux0_reset",
"dsi_core_reset",
"mipi_cal_reset";
status = "disabled";
memory-region = <&fb0_reserved>;
nvidia,disp-sw-soc-chip-id = <0x2350>;
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR &emc>,
<&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
interconnect-names = "dma-mem", "read-1";
#endif #endif
iommus = <&smmu_iso TEGRA234_SID_ISO_NVDISPLAY>;
non-coherent;
nvdisplay-niso {
compatible = "nvidia,tegra234-display-niso";
iommus = <&smmu_niso0 TEGRA234_SID_NVDISPLAY>;
dma-coherent;
};
};
}; };

2039
nv-soc/tegra234-soc-overlay.dtsi
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File diff suppressed because it is too large Load Diff

1091
nv-soc/tegra234-soc-prod-overlay.dtsi
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File diff suppressed because it is too large Load Diff

199
nv-soc/tegra234-soc-safetyservice-fsicom.dtsi
View File

@@ -5,110 +5,101 @@
#include <dt-bindings/memory/tegra234-mc.h> #include <dt-bindings/memory/tegra234-mc.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX reserved-memory {
fragment-fsicom@0 { fsicom_resv: reservation-fsicom {
target-path = "/"; iommu-addresses = <&fsiccplex_com 0x0 0x0 0x0 0xf0000000>,
__overlay__ { <&fsiccplex_com 0x0 0xf1000000 0xffffffff 0x0effffff>;
#endif
reserved-memory {
fsicom_resv: reservation-fsicom {
iommu-addresses = <&fsiccplex_com 0x0 0x0 0x0 0xf0000000>,
<&fsiccplex_com 0x0 0xf1000000 0xffffffff 0x0effffff>;
};
};
fsiccplex_com:fsicom_client {
compatible = "nvidia,tegra234-fsicom-client";
mboxes =
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(2)>,
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>;
mbox-names = "fsi-tx", "fsi-rx";
iommus = <&smmu_niso1 TEGRA234_SID_FSI>;
memory-region = <&fsicom_resv>;
dma-coherent;
status = "disabled";
};
safetyservices_epl_client {
compatible = "nvidia,tegra234-epl-client";
mboxes = <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(0)>;
mbox-names = "epl-tx";
reg = <0x0 0x00110000 0x0 0x4>,
<0x0 0x00110004 0x0 0x4>,
<0x0 0x00120000 0x0 0x4>,
<0x0 0x00120004 0x0 0x4>,
<0x0 0x00130000 0x0 0x4>,
<0x0 0x00130004 0x0 0x4>,
<0x0 0x00140000 0x0 0x4>,
<0x0 0x00140004 0x0 0x4>,
<0x0 0x00150000 0x0 0x4>,
<0x0 0x00150004 0x0 0x4>,
<0x0 0x024e0038 0x0 0x4>;
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR0_SW_ERR_CODE_0 */
client-misc-sw-generic-err0 = "fsicom_client";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR1_SW_ERR_CODE_0 */
client-misc-sw-generic-err1 = "gk20b";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR3_SW_ERR_CODE_0 */
client-misc-sw-generic-err3 = "gk20d";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR4_SW_ERR_CODE_0 */
client-misc-sw-generic-err4 = "gk20e";
status = "disabled";
};
FsiComIvc {
compatible = "nvidia,tegra-fsicom-channels";
status = "disabled";
nChannel = <7>;
channel_0 {
frame-count = <4>;
frame-size = <1024>;
NvSciCh = "nvfsicom_EPD";
};
channel_1 {
frame-count = <30>;
frame-size = <64>;
NvSciCh = "nvfsicom_CcplexApp";
};
channel_2 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_CcplexApp_state_change";
};
channel_3 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_app1";
};
channel_4 {
frame-count = <2>;
frame-size = <512>;
NvSciCh = "nvfsicom_app2";
};
channel_5 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_appGR";
};
channel_6 {
frame-count = <4>;
frame-size = <10240>;
};
};
FsiComClientChConfigEpd {
compatible = "nvidia,tegra-fsicom-EPD";
status = "disabled";
channelid_list = <0>;
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
fsiccplex_com:fsicom_client {
compatible = "nvidia,tegra234-fsicom-client";
mboxes =
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(2)>,
<&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_RX(1)>;
mbox-names = "fsi-tx", "fsi-rx";
iommus = <&smmu_niso1 TEGRA234_SID_FSI>;
memory-region = <&fsicom_resv>;
dma-coherent;
status = "disabled";
};
safetyservices_epl_client {
compatible = "nvidia,tegra234-epl-client";
mboxes = <&hsp_top2 (TEGRA_HSP_MBOX_TYPE_SM | TEGRA_HSP_MBOX_TYPE_SM_128BIT) TEGRA_HSP_SM_TX(0)>;
mbox-names = "epl-tx";
reg = <0x0 0x00110000 0x0 0x4>,
<0x0 0x00110004 0x0 0x4>,
<0x0 0x00120000 0x0 0x4>,
<0x0 0x00120004 0x0 0x4>,
<0x0 0x00130000 0x0 0x4>,
<0x0 0x00130004 0x0 0x4>,
<0x0 0x00140000 0x0 0x4>,
<0x0 0x00140004 0x0 0x4>,
<0x0 0x00150000 0x0 0x4>,
<0x0 0x00150004 0x0 0x4>,
<0x0 0x024e0038 0x0 0x4>;
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR0_SW_ERR_CODE_0 */
client-misc-sw-generic-err0 = "fsicom_client";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR1_SW_ERR_CODE_0 */
client-misc-sw-generic-err1 = "gk20b";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR3_SW_ERR_CODE_0 */
client-misc-sw-generic-err3 = "gk20d";
/* Device driver's name for reporting errors via MISCREG_MISC_EC_ERR4_SW_ERR_CODE_0 */
client-misc-sw-generic-err4 = "gk20e";
status = "disabled";
};
FsiComIvc {
compatible = "nvidia,tegra-fsicom-channels";
status = "disabled";
nChannel = <7>;
channel_0 {
frame-count = <4>;
frame-size = <1024>;
NvSciCh = "nvfsicom_EPD";
};
channel_1 {
frame-count = <30>;
frame-size = <64>;
NvSciCh = "nvfsicom_CcplexApp";
};
channel_2 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_CcplexApp_state_change";
};
channel_3 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_app1";
};
channel_4 {
frame-count = <2>;
frame-size = <512>;
NvSciCh = "nvfsicom_app2";
};
channel_5 {
frame-count = <4>;
frame-size = <64>;
NvSciCh = "nvfsicom_appGR";
};
channel_6 {
frame-count = <4>;
frame-size = <10240>;
};
};
FsiComClientChConfigEpd {
compatible = "nvidia,tegra-fsicom-EPD";
status = "disabled";
channelid_list = <0>;
};
}; };

183
nv-soc/tegra234-soc-thermal-shutdown.dtsi
View File

@@ -4,104 +4,95 @@
#define TEGRA234_THERMAL_SHUTDOWN_TEMP 104500 #define TEGRA234_THERMAL_SHUTDOWN_TEMP 104500
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX thermal-zones {
fragment-t234-thermal-shutdown@0 { cpu-thermal {
target-path = "/"; trips {
__overlay__ { cpu_sw_shutdown: cpu-sw-shutdown {
#endif temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
thermal-zones { hysteresis = <0>;
cpu-thermal { type = "critical";
trips { };
cpu_sw_shutdown: cpu-sw-shutdown { };
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>; };
hysteresis = <0>;
type = "critical"; gpu-thermal {
}; trips {
}; gpu_sw_shutdown: gpu-sw-shutdown {
}; temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
gpu-thermal { type = "critical";
trips { };
gpu_sw_shutdown: gpu-sw-shutdown { };
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>; };
hysteresis = <0>;
type = "critical"; cv0-thermal {
}; trips {
}; cv0_sw_shutdown: cv0-sw-shutdown {
}; temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
cv0-thermal { type = "critical";
trips { };
cv0_sw_shutdown: cv0-sw-shutdown { };
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>; };
hysteresis = <0>;
type = "critical"; cv1-thermal {
}; trips {
}; cv1_sw_shutdown: cv1-sw-shutdown {
}; temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
cv1-thermal { type = "critical";
trips { };
cv1_sw_shutdown: cv1-sw-shutdown { };
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>; };
hysteresis = <0>;
type = "critical"; cv2-thermal {
}; trips {
}; cv2_sw_shutdown: cv2-sw-shutdown {
}; temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
cv2-thermal { type = "critical";
trips { };
cv2_sw_shutdown: cv2-sw-shutdown { };
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>; };
hysteresis = <0>;
type = "critical"; soc0-thermal {
}; trips {
}; soc0_sw_shutdown: soc0-sw-shutdown {
}; temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
soc0-thermal { type = "critical";
trips { };
soc0_sw_shutdown: soc0-sw-shutdown { };
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>; };
hysteresis = <0>;
type = "critical"; soc1-thermal {
}; trips {
}; soc1_sw_shutdown: soc1-sw-shutdown {
}; temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
soc1-thermal { type = "critical";
trips { };
soc1_sw_shutdown: soc1-sw-shutdown { };
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>; };
hysteresis = <0>;
type = "critical"; soc2-thermal {
}; trips {
}; soc2_sw_shutdown: soc2-sw-shutdown {
}; temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
soc2-thermal { type = "critical";
trips { };
soc2_sw_shutdown: soc2-sw-shutdown { };
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>; };
hysteresis = <0>;
type = "critical"; tj-thermal {
}; trips {
}; tj_sw_shutdown: tj-sw-shutdown {
}; temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
tj-thermal { type = "critical";
trips {
tj_sw_shutdown: tj-sw-shutdown {
temperature = <TEGRA234_THERMAL_SHUTDOWN_TEMP>;
hysteresis = <0>;
type = "critical";
};
};
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

431
nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi
View File

@@ -6,226 +6,217 @@
#define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000 #define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX bus@0 {
fragment-t234-thermal-slowdown-cluster@0 { gpu@17000000 {
target-path = "/"; #cooling-cells = <2>;
__overlay__ { };
#endif };
bus@0 {
gpu@17000000 { cpus{
#cooling-cells = <2>; cpu@0 {
}; #cooling-cells = <2>;
}; };
cpus{ cpu@10000 {
cpu@0 { #cooling-cells = <2>;
#cooling-cells = <2>; };
};
cpu@20000 {
cpu@10000 { #cooling-cells = <2>;
#cooling-cells = <2>; };
}; };
cpu@20000 { thermal-zones {
#cooling-cells = <2>; cpu-thermal {
}; trips {
}; cpu_sw_slowdown: cpu-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
thermal-zones { hysteresis = <0>;
cpu-thermal { type = "passive";
trips { };
cpu_sw_slowdown: cpu-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&cpu_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
map-cpufreq { };
trip = <&cpu_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&cpu_sw_slowdown>;
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&cpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; gpu-thermal {
}; trips {
}; gpu_sw_slowdown: gpu-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
gpu-thermal { type = "passive";
trips { };
gpu_sw_slowdown: gpu-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&gpu_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
map-cpufreq { };
trip = <&gpu_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&gpu_sw_slowdown>;
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&gpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cv0-thermal {
}; trips {
}; cv0_sw_slowdown: cv0-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
cv0-thermal { type = "passive";
trips { };
cv0_sw_slowdown: cv0-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&cv0_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
map-cpufreq { };
trip = <&cv0_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&cv0_sw_slowdown>;
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&cv0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cv1-thermal {
}; trips {
}; cv1_sw_slowdown: cv1-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
cv1-thermal { type = "passive";
trips { };
cv1_sw_slowdown: cv1-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&cv1_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
map-cpufreq { };
trip = <&cv1_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&cv1_sw_slowdown>;
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&cv1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cv2-thermal {
}; trips {
}; cv2_sw_slowdown: cv2-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
cv2-thermal { type = "passive";
trips { };
cv2_sw_slowdown: cv2-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&cv2_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
map-cpufreq { };
trip = <&cv2_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&cv2_sw_slowdown>;
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&cv2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; soc0-thermal {
}; trips {
}; soc0_sw_slowdown: soc0-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
soc0-thermal { type = "passive";
trips { };
soc0_sw_slowdown: soc0-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&soc0_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
map-cpufreq { };
trip = <&soc0_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&soc0_sw_slowdown>;
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&soc0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; soc1-thermal {
}; trips {
}; soc1_sw_slowdown: soc1-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
soc1-thermal { type = "passive";
trips { };
soc1_sw_slowdown: soc1-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&soc1_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
map-cpufreq { };
trip = <&soc1_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&soc1_sw_slowdown>;
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&soc1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; soc2-thermal {
}; trips {
}; soc2_sw_slowdown: soc2-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
soc2-thermal { type = "passive";
trips { };
soc2_sw_slowdown: soc2-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&soc2_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
map-cpufreq { };
trip = <&soc2_sw_slowdown>;
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&soc2_sw_slowdown>;
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq {
trip = <&soc2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

503
nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi
View File

@@ -6,262 +6,253 @@
#define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000 #define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX bus@0 {
fragment-t234-thermal-slowdown-corepair@0 { gpu@17000000 {
target-path = "/"; #cooling-cells = <2>;
__overlay__ { };
#endif };
bus@0 {
gpu@17000000 { cpus{
#cooling-cells = <2>; cpu@0 {
}; #cooling-cells = <2>;
}; };
cpus{ cpu@200 {
cpu@0 { #cooling-cells = <2>;
#cooling-cells = <2>; };
};
cpu@10000 {
cpu@200 { #cooling-cells = <2>;
#cooling-cells = <2>; };
};
cpu@10200 {
cpu@10000 { #cooling-cells = <2>;
#cooling-cells = <2>; };
};
cpu@20000 {
cpu@10200 { #cooling-cells = <2>;
#cooling-cells = <2>; };
};
cpu@20200 {
cpu@20000 { #cooling-cells = <2>;
#cooling-cells = <2>; };
}; };
cpu@20200 { thermal-zones {
#cooling-cells = <2>; cpu-thermal {
}; trips {
}; cpu_sw_slowdown: cpu-sw-slowdown {
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
thermal-zones { hysteresis = <0>;
cpu-thermal { type = "passive";
trips { };
cpu_sw_slowdown: cpu-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&cpu_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
map-cpufreq { <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
trip = <&cpu_sw_slowdown>; <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, };
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&cpu_sw_slowdown>;
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&cpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; gpu-thermal {
}; trips {
}; gpu_sw_slowdown: gpu-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
gpu-thermal { type = "passive";
trips { };
gpu_sw_slowdown: gpu-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&gpu_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
map-cpufreq { <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
trip = <&gpu_sw_slowdown>; <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, };
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&gpu_sw_slowdown>;
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&gpu_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cv0-thermal {
}; trips {
}; cv0_sw_slowdown: cv0-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
cv0-thermal { type = "passive";
trips { };
cv0_sw_slowdown: cv0-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&cv0_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
map-cpufreq { <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
trip = <&cv0_sw_slowdown>; <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, };
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&cv0_sw_slowdown>;
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&cv0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cv1-thermal {
}; trips {
}; cv1_sw_slowdown: cv1-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
cv1-thermal { type = "passive";
trips { };
cv1_sw_slowdown: cv1-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&cv1_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
map-cpufreq { <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
trip = <&cv1_sw_slowdown>; <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, };
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&cv1_sw_slowdown>;
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&cv1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cv2-thermal {
}; trips {
}; cv2_sw_slowdown: cv2-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
cv2-thermal { type = "passive";
trips { };
cv2_sw_slowdown: cv2-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&cv2_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
map-cpufreq { <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
trip = <&cv2_sw_slowdown>; <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, };
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&cv2_sw_slowdown>;
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&cv2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; soc0-thermal {
}; trips {
}; soc0_sw_slowdown: soc0-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
soc0-thermal { type = "passive";
trips { };
soc0_sw_slowdown: soc0-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&soc0_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
map-cpufreq { <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
trip = <&soc0_sw_slowdown>; <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, };
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&soc0_sw_slowdown>;
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&soc0_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; soc1-thermal {
}; trips {
}; soc1_sw_slowdown: soc1-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
soc1-thermal { type = "passive";
trips { };
soc1_sw_slowdown: soc1-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&soc1_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
map-cpufreq { <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
trip = <&soc1_sw_slowdown>; <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, };
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&soc1_sw_slowdown>;
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq { };
trip = <&soc1_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; soc2-thermal {
}; trips {
}; soc2_sw_slowdown: soc2-sw-slowdown {
}; temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>;
soc2-thermal { type = "passive";
trips { };
soc2_sw_slowdown: soc2-sw-slowdown { };
temperature = <TEGRA234_THERMAL_SLOWDOWN_TEMP>;
hysteresis = <0>; cooling-maps {
type = "passive"; map-cpufreq {
}; trip = <&soc2_sw_slowdown>;
}; cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-maps { <&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
map-cpufreq { <&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
trip = <&soc2_sw_slowdown>; <&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
cooling-device = <&cpu0_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, };
<&cpu1_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, map-devfreq {
<&cpu2_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, trip = <&soc2_sw_slowdown>;
<&cpu2_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
};
map-devfreq {
trip = <&soc2_sw_slowdown>;
cooling-device = <&ga10b THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

81
nv-soc/tegra234-soc-thermal.dtsi
View File

@@ -4,59 +4,50 @@
#define TEGRA234_THERMAL_POLLING_DELAY 1000 #define TEGRA234_THERMAL_POLLING_DELAY 1000
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX thermal-zones {
fragment-t234-thermal@0 { cpu-thermal {
target-path = "/"; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
__overlay__ { polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
#endif };
thermal-zones {
cpu-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
gpu-thermal { gpu-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
}; };
cv0-thermal { cv0-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
}; };
cv1-thermal { cv1-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
}; };
cv2-thermal { cv2-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
}; };
soc0-thermal { soc0-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
}; };
soc1-thermal { soc1-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
}; };
soc2-thermal { soc2-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
}; };
tj-thermal { tj-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
};
};
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };