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arm64: tegra: Use correct format for clocks property

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phandle and clock specifier pairs should be enclosed in angular
brackets.

Bug 4037899
Bug 4707773

Change-Id: I07fcce3729ebf74d17847f6502b87438b0548cbb
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3035766
(cherry picked from commit 089ac40a2e)
Signed-off-by: Vedant Deshpande <vedantd@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3172822
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
This commit is contained in:
Thierry Reding
2023-08-17 16:14:05 +02:00
committed by mobile promotions
parent 1ffe07b61c
commit 941cde9d73
1 changed files with 16 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
tegra234.dtsi
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@@ -2783,8 +2783,8 @@
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C1
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C1>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@@ -2802,8 +2802,8 @@
#size-cells = <0>;
status = "disabled";
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C3
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C3>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@@ -2821,8 +2821,8 @@
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C4
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C4>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@@ -2840,8 +2840,8 @@
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C6
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C6>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@@ -2859,8 +2859,8 @@
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C7
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C7>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@@ -2885,8 +2885,8 @@
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C9
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C9>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
@@ -3868,8 +3868,8 @@
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clocks = <&bpmp TEGRA234_CLK_I2C2
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C2>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
@@ -3887,8 +3887,8 @@
#size-cells = <0>;
status = "disabled";
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C8
&bpmp TEGRA234_CLK_PLLP_OUT0>;
clocks = <&bpmp TEGRA234_CLK_I2C8>,
<&bpmp TEGRA234_CLK_PLLP_OUT0>;
clock-names = "div-clk", "parent";
assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;