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nv-public:P3762: Fix probe fail of Hawks during boot.

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1. Made all sensors of Hawks as master sensors so any sensor is capable
to program SERIALIZERS i2c address translation during probe time
i.e first come first basis.So, We wont miss or skip SERIALIZERS i2c trans.
2. Changed i2c bus 8 freq to 400khz

Bug 4510846

Change-Id: Ia627ebd430709efac64ec849b37167c88b5cf012
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3112253
Tested-by: Praveen AC <pac@nvidia.com>
Tested-by: Shubham Chandra <shubhamc@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Shubham Chandra <shubhamc@nvidia.com>
Reviewed-by: Ankur Pawar <ankurp@nvidia.com>
Reviewed-by: Praveen AC <pac@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
This commit is contained in:
Praveen AC
2024-04-09 16:13:44 +00:00
committed by mobile promotions
parent 748f517742
commit 9944294772
2 changed files with 5 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
overlay/tegra234-p3737-camera-p3762-a00-overlay.dts
View File

@@ -177,7 +177,7 @@
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "c";
channel = "a";
has-eeprom;
eeprom-addr = <0x40>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
@@ -215,7 +215,7 @@
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "c";
channel = "a";
has-eeprom;
eeprom-addr = <0x15>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
@@ -247,7 +247,7 @@
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "c";
channel = "a";
has-eeprom;
eeprom-addr = <0x44>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
@@ -279,7 +279,7 @@
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "c";
channel = "a";
has-eeprom;
eeprom-addr = <0x46>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;

2
tegra234.dtsi
View File

@@ -806,7 +806,7 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
clock-frequency = <100000>;
clock-frequency = <400000>;
clocks = <&bpmp TEGRA234_CLK_I2C9
&bpmp TEGRA234_CLK_PLLP_OUT0>;
assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;