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include: dt-bindings: Add headers for nvidia-oot

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Add DT binding headers, non-upstreamed version, which
are used for SOC and platform DTS/DTSI. These headers
are in staging state and taken from the
     hardware/nvidia/soc/generic-dts/tegra/include/nvidia-oot.

Bug 4078385

Change-Id: Ia482b55e44c708ce5cab7d1fbcb8abfc07f4e440
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
This commit is contained in:
Laxman Dewangan
2023-04-19 17:59:46 +00:00
parent 493823811d
commit a7a7af00d8
4 changed files with 562 additions and 0 deletions
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163
include/nvidia-oot/dt-bindings/interrupt/tegra234-irq.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef _DT_BINDINGS_INTERRUPT_TEGRAT234_IRQ_H
#define _DT_BINDINGS_INTERRUPT_TEGRAT234_IRQ_H
#define TEGRA234_IRQ_I2C1 25
#define TEGRA234_IRQ_I2C2 26
#define TEGRA234_IRQ_I2C3 27
#define TEGRA234_IRQ_I2C4 28
#define TEGRA234_IRQ_I2C5 29
#define TEGRA234_IRQ_I2C6 30
#define TEGRA234_IRQ_I2C7 31
#define TEGRA234_IRQ_I2C8 32
#define TEGRA234_IRQ_I2C9 33
#define TEGRA234_IRQ_UFSHC 44
#define TEGRA234_IRQ_SDMMC1 62
#define TEGRA234_IRQ_SDMMC3 64
#define TEGRA234_IRQ_SDMMC4 65
#define TEGRA234_IRQ_UARTA 112
#define TEGRA234_IRQ_UARTB 113
#define TEGRA234_IRQ_UARTC 114
#define TEGRA234_IRQ_UARTD 115
#define TEGRA234_IRQ_UARTE 116
#define TEGRA234_IRQ_UARTF 117
#define TEGRA234_IRQ_UARTG 118
#define TEGRA234_IRQ_UARTH 207
#define TEGRA234_IRQ_UARTI 285
#define TEGRA234_IRQ_UARTJ 286
#define TEGRA234_IRQ_EQOS_TX0 186
#define TEGRA234_IRQ_EQOS_TX1 187
#define TEGRA234_IRQ_EQOS_TX2 188
#define TEGRA234_IRQ_EQOS_TX3 189
#define TEGRA234_IRQ_EQOS_RX0 190
#define TEGRA234_IRQ_EQOS_RX1 191
#define TEGRA234_IRQ_TACH0 192
#define TEGRA234_IRQ_TACH1 193
#define TEGRA234_IRQ_EQOS_COMMON 194
#define TEGRA234_IRQ_EQOS_POWER 195
#define TEGRA234_IRQ_SATA 197
#define TEGRA234_IRQ_ACTMON 210
#define TEGRA234_IRQ_GPIO0_0 288
#define TEGRA234_IRQ_GPIO0_1 289
#define TEGRA234_IRQ_GPIO0_2 290
#define TEGRA234_IRQ_GPIO0_3 291
#define TEGRA234_IRQ_GPIO0_4 292
#define TEGRA234_IRQ_GPIO0_5 293
#define TEGRA234_IRQ_GPIO0_6 294
#define TEGRA234_IRQ_GPIO0_7 295
#define TEGRA234_IRQ_GPIO1_0 296
#define TEGRA234_IRQ_GPIO1_1 297
#define TEGRA234_IRQ_GPIO1_2 298
#define TEGRA234_IRQ_GPIO1_3 299
#define TEGRA234_IRQ_GPIO1_4 300
#define TEGRA234_IRQ_GPIO1_5 301
#define TEGRA234_IRQ_GPIO1_6 302
#define TEGRA234_IRQ_GPIO1_7 303
#define TEGRA234_IRQ_GPIO2_0 304
#define TEGRA234_IRQ_GPIO2_1 305
#define TEGRA234_IRQ_GPIO2_2 306
#define TEGRA234_IRQ_GPIO2_3 307
#define TEGRA234_IRQ_GPIO2_4 308
#define TEGRA234_IRQ_GPIO2_5 309
#define TEGRA234_IRQ_GPIO2_6 310
#define TEGRA234_IRQ_GPIO2_7 311
#define TEGRA234_IRQ_GPIO3_0 312
#define TEGRA234_IRQ_GPIO3_1 313
#define TEGRA234_IRQ_GPIO3_2 314
#define TEGRA234_IRQ_GPIO3_3 315
#define TEGRA234_IRQ_GPIO3_4 316
#define TEGRA234_IRQ_GPIO3_5 317
#define TEGRA234_IRQ_GPIO3_6 318
#define TEGRA234_IRQ_GPIO3_7 319
#define TEGRA234_IRQ_GPIO4_0 320
#define TEGRA234_IRQ_GPIO4_1 321
#define TEGRA234_IRQ_GPIO4_2 322
#define TEGRA234_IRQ_GPIO4_3 323
#define TEGRA234_IRQ_GPIO4_4 324
#define TEGRA234_IRQ_GPIO4_5 325
#define TEGRA234_IRQ_GPIO4_6 326
#define TEGRA234_IRQ_GPIO4_7 327
#define TEGRA234_IRQ_GPIO5_0 328
#define TEGRA234_IRQ_GPIO5_1 329
#define TEGRA234_IRQ_GPIO5_2 330
#define TEGRA234_IRQ_GPIO5_3 331
#define TEGRA234_IRQ_GPIO5_4 332
#define TEGRA234_IRQ_GPIO5_5 333
#define TEGRA234_IRQ_GPIO5_6 334
#define TEGRA234_IRQ_GPIO5_7 335
#define TEGRA234_IRQ_AON_GPIO_0 56
#define TEGRA234_IRQ_AON_GPIO_1 57
#define TEGRA234_IRQ_AON_GPIO_2 58
#define TEGRA234_IRQ_AON_GPIO_3 59
#define TEGRA234_IRQ_BPMP_WDT_REMOTE 14
#define TEGRA234_IRQ_SPE_WDT_REMOTE 15
#define TEGRA234_IRQ_SCE_WDT_REMOTE 16
#define TEGRA234_IRQ_TOP_WDT_REMOTE 17
#define TEGRA234_IRQ_AOWDT_REMOTE 18
#define TEGRA234_IRQ_RCE_WDT_REMOTE 19
#define TEGRA234_IRQ_APE_WDT_REMOTE 20
#define TEGRA234_IRQ_TOP0_HSP_SHARED_0 120
#define TEGRA234_IRQ_TOP0_HSP_SHARED_1 121
#define TEGRA234_IRQ_TOP0_HSP_SHARED_2 122
#define TEGRA234_IRQ_TOP0_HSP_SHARED_3 123
#define TEGRA234_IRQ_TOP0_HSP_SHARED_4 124
#define TEGRA234_IRQ_TOP0_HSP_SHARED_5 125
#define TEGRA234_IRQ_TOP0_HSP_SHARED_6 126
#define TEGRA234_IRQ_TOP0_HSP_SHARED_7 127
#define TEGRA234_IRQ_TOP1_HSP_SHARED_0 128
#define TEGRA234_IRQ_TOP1_HSP_SHARED_1 129
#define TEGRA234_IRQ_TOP1_HSP_SHARED_2 130
#define TEGRA234_IRQ_TOP1_HSP_SHARED_3 131
#define TEGRA234_IRQ_TOP1_HSP_SHARED_4 132
#define TEGRA234_IRQ_AON_HSP_SHARED_1 133
#define TEGRA234_IRQ_AON_HSP_SHARED_2 134
#define TEGRA234_IRQ_AON_HSP_SHARED_3 135
#define TEGRA234_IRQ_AON_HSP_SHARED_4 136
#define TEGRA234_IRQ_BPMP_HSP_SHARED_1 137
#define TEGRA234_IRQ_BPMP_HSP_SHARED_2 138
#define TEGRA234_IRQ_BPMP_HSP_SHARED_3 139
#define TEGRA234_IRQ_BPMP_HSP_SHARED_4 140
#define TEGRA234_IRQ_SCE_HSP_SHARED_1 141
#define TEGRA234_IRQ_SCE_HSP_SHARED_2 142
#define TEGRA234_IRQ_SCE_HSP_SHARED_3 143
#define TEGRA234_IRQ_SCE_HSP_SHARED_4 144
#define TEGRA234_IRQ_RCE_HSP_SHARED_1 182
#define TEGRA234_IRQ_RCE_HSP_SHARED_2 183
#define TEGRA234_IRQ_RCE_HSP_SHARED_3 184
#define TEGRA234_IRQ_RCE_HSP_SHARED_4 185
#define TEGRA234_IRQ_PMIC_EXT_INTR 209
#define TEGRA234_IRQ_HSIO_L0_P2U 336
#define TEGRA234_IRQ_HSIO_L1_P2U 337
#define TEGRA234_IRQ_HSIO_L2_P2U 338
#define TEGRA234_IRQ_HSIO_L3_P2U 339
#define TEGRA234_IRQ_HSIO_L4_P2U 340
#define TEGRA234_IRQ_HSIO_L5_P2U 341
#define TEGRA234_IRQ_HSIO_L6_P2U 342
#define TEGRA234_IRQ_HSIO_L7_P2U 343
#define TEGRA234_IRQ_NVHS_L0_P2U 344
#define TEGRA234_IRQ_NVHS_L1_P2U 345
#define TEGRA234_IRQ_NVHS_L2_P2U 346
#define TEGRA234_IRQ_NVHS_L3_P2U 347
#define TEGRA234_IRQ_NVHS_L4_P2U 348
#define TEGRA234_IRQ_NVHS_L5_P2U 349
#define TEGRA234_IRQ_NVHS_L6_P2U 350
#define TEGRA234_IRQ_NVHS_L7_P2U 351
#define TEGRA234_IRQ_GBE_L0_P2U 203
#define TEGRA234_IRQ_GBE_L1_P2U 220
#define TEGRA234_IRQ_GBE_L2_P2U 221
#define TEGRA234_IRQ_GBE_L3_P2U 222
#define TEGRA234_IRQ_GBE_L4_P2U 108
#define TEGRA234_IRQ_GBE_L5_P2U 109
#define TEGRA234_IRQ_GBE_L6_P2U 110
#define TEGRA234_IRQ_GBE_L7_P2U 111
#endif

34
include/nvidia-oot/dt-bindings/p2u/tegra234-p2u.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef _DT_BINDINGS_P2U_TEGRAT234_P2U_H
#define _DT_BINDINGS_P2U_TEGRAT234_P2U_H
#define TEGRA234_P2U_LANE_ID0 0
#define TEGRA234_P2U_LANE_ID1 1
#define TEGRA234_P2U_LANE_ID2 2
#define TEGRA234_P2U_LANE_ID3 3
#define TEGRA234_P2U_LANE_ID4 4
#define TEGRA234_P2U_LANE_ID5 5
#define TEGRA234_P2U_LANE_ID6 6
#define TEGRA234_P2U_LANE_ID7 7
#define TEGRA234_P2U_LANE_ID8 8
#define TEGRA234_P2U_LANE_ID9 9
#define TEGRA234_P2U_LANE_ID10 10
#define TEGRA234_P2U_LANE_ID11 11
#define TEGRA234_P2U_LANE_ID12 12
#define TEGRA234_P2U_LANE_ID13 13
#define TEGRA234_P2U_LANE_ID14 14
#define TEGRA234_P2U_LANE_ID15 15
#define TEGRA234_P2U_LANE_ID16 16
#define TEGRA234_P2U_LANE_ID17 17
#define TEGRA234_P2U_LANE_ID18 18
#define TEGRA234_P2U_LANE_ID19 19
#define TEGRA234_P2U_LANE_ID20 20
#define TEGRA234_P2U_LANE_ID21 21
#define TEGRA234_P2U_LANE_ID22 22
#define TEGRA234_P2U_LANE_ID23 23
#endif /* _DT_BINDINGS_P2U_TEGRAT234_P2U_H */

346
include/nvidia-oot/dt-bindings/sound/tegra-asoc-dais.h Normal file
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// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#ifndef __DT_TEGRA_ASOC_DAIS_H
#define __DT_TEGRA_ASOC_DAIS_H
/*
* DAI links can have one of these value
* PCM_LINK : optional, if nothing is specified link is treated as PCM link
* COMPR_LINK : required, if link is used with compress device
* C2C_LINK : required, for any other back end codec-to-codec links
*/
#define PCM_LINK 0
#define COMPR_LINK 1
#define C2C_LINK 2
/*
* Following DAI indices are derived from respective module drivers.
* Thus below values have to be in sync with the DAI arrays defined
* in the drivers.
*/
#define XBAR_ADMAIF1 0
#define XBAR_ADMAIF2 1
#define XBAR_ADMAIF3 2
#define XBAR_ADMAIF4 3
#define XBAR_ADMAIF5 4
#define XBAR_ADMAIF6 5
#define XBAR_ADMAIF7 6
#define XBAR_ADMAIF8 7
#define XBAR_ADMAIF9 8
#define XBAR_ADMAIF10 9
#define XBAR_ADMAIF11 10
#define XBAR_ADMAIF12 11
#define XBAR_ADMAIF13 12
#define XBAR_ADMAIF14 13
#define XBAR_ADMAIF15 14
#define XBAR_ADMAIF16 15
#define XBAR_ADMAIF17 16
#define XBAR_ADMAIF18 17
#define XBAR_ADMAIF19 18
#define XBAR_ADMAIF20 19
#define XBAR_I2S1 20
#define XBAR_I2S2 21
#define XBAR_I2S3 22
#define XBAR_I2S4 23
#define XBAR_I2S5 24
#define XBAR_I2S6 25
#define XBAR_DMIC1 26
#define XBAR_DMIC2 27
#define XBAR_DMIC3 28
#define XBAR_DMIC4 29
#define XBAR_DSPK1 30
#define XBAR_DSPK2 31
#define XBAR_SFC1_RX 32
/*
* TODO As per downstream kernel code there will be routing issue
* if DAI names are updated for SFC, MVC and OPE input and
* output. Due to that using single DAI with same name as downstream
* kernel for input and output and added output DAIs just to keep
* similar to upstream kernel, so that it will be easy to upstream
* later.
*
* Once the routing changes are done for above mentioned modules,
* use the commented output dai index and define output dai
* links in tegra186-audio-graph.dtsi
*/
#if 0
#define XBAR_SFC1_TX 33
#define XBAR_SFC2_TX 35
#define XBAR_SFC3_TX 37
#define XBAR_SFC4_TX 39
#define XBAR_MVC1_TX 41
#define XBAR_MVC2_TX 43
#define XBAR_OPE1_TX 113
#else
#define XBAR_SFC1_TX XBAR_SFC1_RX
#define XBAR_SFC2_TX XBAR_SFC2_RX
#define XBAR_SFC3_TX XBAR_SFC3_RX
#define XBAR_SFC4_TX XBAR_SFC4_RX
#define XBAR_MVC1_TX XBAR_MVC1_RX
#define XBAR_MVC2_TX XBAR_MVC2_RX
#define XBAR_OPE1_TX XBAR_OPE1_RX
#endif
#define XBAR_SFC2_RX 34
#define XBAR_SFC3_RX 36
#define XBAR_SFC4_RX 38
#define XBAR_MVC1_RX 40
#define XBAR_MVC2_RX 42
#define XBAR_AMX1_IN1 44
#define XBAR_AMX1_IN2 45
#define XBAR_AMX1_IN3 46
#define XBAR_AMX1_IN4 47
#define XBAR_AMX1_OUT 48
#define XBAR_AMX2_IN1 49
#define XBAR_AMX2_IN2 50
#define XBAR_AMX2_IN3 51
#define XBAR_AMX2_IN4 52
#define XBAR_AMX2_OUT 53
#define XBAR_AMX3_IN1 54
#define XBAR_AMX3_IN2 55
#define XBAR_AMX3_IN3 56
#define XBAR_AMX3_IN4 57
#define XBAR_AMX3_OUT 58
#define XBAR_AMX4_IN1 59
#define XBAR_AMX4_IN2 60
#define XBAR_AMX4_IN3 61
#define XBAR_AMX4_IN4 62
#define XBAR_AMX4_OUT 63
#define XBAR_ADX1_IN 64
#define XBAR_ADX1_OUT1 65
#define XBAR_ADX1_OUT2 66
#define XBAR_ADX1_OUT3 67
#define XBAR_ADX1_OUT4 68
#define XBAR_ADX2_IN 69
#define XBAR_ADX2_OUT1 70
#define XBAR_ADX2_OUT2 71
#define XBAR_ADX2_OUT3 72
#define XBAR_ADX2_OUT4 73
#define XBAR_ADX3_IN 74
#define XBAR_ADX3_OUT1 75
#define XBAR_ADX3_OUT2 76
#define XBAR_ADX3_OUT3 77
#define XBAR_ADX3_OUT4 78
#define XBAR_ADX4_IN 79
#define XBAR_ADX4_OUT1 80
#define XBAR_ADX4_OUT2 81
#define XBAR_ADX4_OUT3 82
#define XBAR_ADX4_OUT4 83
#define XBAR_MIXER_IN1 84
#define XBAR_MIXER_IN2 85
#define XBAR_MIXER_IN3 86
#define XBAR_MIXER_IN4 87
#define XBAR_MIXER_IN5 88
#define XBAR_MIXER_IN6 89
#define XBAR_MIXER_IN7 90
#define XBAR_MIXER_IN8 91
#define XBAR_MIXER_IN9 92
#define XBAR_MIXER_IN10 93
#define XBAR_MIXER_OUT1 94
#define XBAR_MIXER_OUT2 95
#define XBAR_MIXER_OUT3 96
#define XBAR_MIXER_OUT4 97
#define XBAR_MIXER_OUT5 98
#define XBAR_ASRC_IN1 99
#define XBAR_ASRC_OUT1 100
#define XBAR_ASRC_IN2 101
#define XBAR_ASRC_OUT2 102
#define XBAR_ASRC_IN3 103
#define XBAR_ASRC_OUT3 104
#define XBAR_ASRC_IN4 105
#define XBAR_ASRC_OUT4 106
#define XBAR_ASRC_IN5 107
#define XBAR_ASRC_OUT5 108
#define XBAR_ASRC_IN6 109
#define XBAR_ASRC_OUT6 110
#define XBAR_ASRC_IN7 111
#define XBAR_OPE1_RX 112
#define XBAR_AFC1 114
#define XBAR_AFC2 115
#define XBAR_AFC3 116
#define XBAR_AFC4 117
#define XBAR_AFC5 118
#define XBAR_AFC6 119
#define XBAR_SPKPROT 120
#define XBAR_IQC1_1 121
#define XBAR_IQC1_2 122
#define XBAR_IQC2_1 123
#define XBAR_IQC2_2 124
#define XBAR_ARAD 125
/* ADMAIF DAIs */
#define ADMAIF1 0
#define ADMAIF2 1
#define ADMAIF3 2
#define ADMAIF4 3
#define ADMAIF5 4
#define ADMAIF6 5
#define ADMAIF7 6
#define ADMAIF8 7
#define ADMAIF9 8
#define ADMAIF10 9
#define ADMAIF11 10
#define ADMAIF12 11
#define ADMAIF13 12
#define ADMAIF14 13
#define ADMAIF15 14
#define ADMAIF16 15
#define ADMAIF17 16
#define ADMAIF18 17
#define ADMAIF19 18
#define ADMAIF20 19
/*
* ADMAIF_FIFO: DAIs used for DAI links between ADMAIF and ADSP.
* Offset depends on the number of ADMAIF channels for a chip.
* The DAI indices for these are derived from below offsets.
*/
#define TEGRA186_ADMAIF_FIFO_OFFSET 20
/*
* ADMAIF_CIF: DAIs used for codec-to-codec links between ADMAIF and XBAR.
* Offset depends on the number of ADMAIF channels for a chip.
* The DAI indices for these are derived from below offsets.
*/
#define TEGRA186_ADMAIF_CIF_OFFSET 40
/* I2S */
#define I2S_CIF 0
#define I2S_DAP 1
#define I2S_DUMMY 2
/* DMIC */
#define DMIC_CIF 0
#define DMIC_DAP 1
#define DMIC_DUMMY 2
/* DSPK */
#define DSPK_CIF 0
#define DSPK_DAP 1
#define DSPK_DUMMY 2
/* SFC */
#define SFC_IN 0
#define SFC_OUT 1
/* MIXER */
#define MIXER_IN1 0
#define MIXER_IN2 1
#define MIXER_IN3 2
#define MIXER_IN4 3
#define MIXER_IN5 4
#define MIXER_IN6 5
#define MIXER_IN7 6
#define MIXER_IN8 7
#define MIXER_IN9 8
#define MIXER_IN10 9
#define MIXER_OUT1 10
#define MIXER_OUT2 11
#define MIXER_OUT3 12
#define MIXER_OUT4 13
#define MIXER_OUT5 14
/* AFC */
#define AFC_IN 0
#define AFC_OUT 1
/* OPE */
#define OPE_IN 0
#define OPE_OUT 1
/* MVC */
#define MVC_IN 0
#define MVC_OUT 1
/* AMX */
#define AMX_IN1 0
#define AMX_IN2 1
#define AMX_IN3 2
#define AMX_IN4 3
#define AMX_OUT 4
/* ADX */
#define ADX_OUT1 0
#define ADX_OUT2 1
#define ADX_OUT3 2
#define ADX_OUT4 3
#define ADX_IN 4
/* ASRC */
#define ASRC_IN1 0
#define ASRC_IN2 1
#define ASRC_IN3 2
#define ASRC_IN4 3
#define ASRC_IN5 4
#define ASRC_IN6 5
#define ASRC_IN7 6
#define ASRC_OUT1 7
#define ASRC_OUT2 8
#define ASRC_OUT3 9
#define ASRC_OUT4 10
#define ASRC_OUT5 11
#define ASRC_OUT6 12
/* ARAD */
#define ARAD 0
/* ADSP */
#define ADSP_FE1 0
#define ADSP_FE2 1
#define ADSP_FE3 2
#define ADSP_FE4 3
#define ADSP_FE5 4
#define ADSP_FE6 5
#define ADSP_FE7 6
#define ADSP_FE8 7
#define ADSP_FE9 8
#define ADSP_FE10 9
#define ADSP_FE11 10
#define ADSP_FE12 11
#define ADSP_FE13 12
#define ADSP_FE14 13
#define ADSP_FE15 14
#define ADSP_EAVB_CODEC 15
#define ADSP_ADMAIF1 16
#define ADSP_ADMAIF2 17
#define ADSP_ADMAIF3 18
#define ADSP_ADMAIF4 19
#define ADSP_ADMAIF5 20
#define ADSP_ADMAIF6 21
#define ADSP_ADMAIF7 22
#define ADSP_ADMAIF8 23
#define ADSP_ADMAIF9 24
#define ADSP_ADMAIF10 25
#define ADSP_ADMAIF11 26
#define ADSP_ADMAIF12 27
#define ADSP_ADMAIF13 28
#define ADSP_ADMAIF14 29
#define ADSP_ADMAIF15 30
#define ADSP_ADMAIF16 31
#define ADSP_ADMAIF17 32
#define ADSP_ADMAIF18 33
#define ADSP_ADMAIF19 34
#define ADSP_ADMAIF20 35
#define ADSP_PCM1 36
#define ADSP_PCM2 37
#define ADSP_PCM3 38
#define ADSP_PCM4 39
#define ADSP_PCM5 40
#define ADSP_PCM6 41
#define ADSP_PCM7 42
#define ADSP_PCM8 43
#define ADSP_PCM9 44
#define ADSP_PCM10 45
#define ADSP_PCM11 46
#define ADSP_PCM12 47
#define ADSP_PCM13 48
#define ADSP_PCM14 49
#define ADSP_PCM15 50
#define ADSP_COMPR1 51
#define ADSP_COMPR2 52
#define ADSP_EAVB 53
#endif

19
include/nvidia-oot/dt-bindings/thermal/tegra234-bpmp-thermal-oot.h Normal file
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/*
* This header provides constants for binding nvidia,tegra234-bpmp-thermal.
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H
#define _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H
#define TEGRA234_THERMAL_ZONE_CPU 0
#define TEGRA234_THERMAL_ZONE_GPU 1
#define TEGRA234_THERMAL_ZONE_CV0 2
#define TEGRA234_THERMAL_ZONE_CV1 3
#define TEGRA234_THERMAL_ZONE_CV2 4
#define TEGRA234_THERMAL_ZONE_SOC0 5
#define TEGRA234_THERMAL_ZONE_SOC1 6
#define TEGRA234_THERMAL_ZONE_SOC2 7
#define TEGRA234_THERMAL_ZONE_TJ_MAX 8
#define TEGRA234_THERMAL_ZONE_COUNT 9
#endif