From a84636dac2efc607b02273f74d133369d9e1569c Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Fri, 7 Apr 2023 09:40:32 +0000 Subject: [PATCH] soc: tegra234: dtsi: Sync nodes matching with mainline v6.3-rc5 Match the nodes of the tegra234.dtsi wil the mainline V6.3-rc5. This patch matches: - Property sequence - removing of iommu property from i2c nodes of base and moving to overlay. Bug 4057304 Change-Id: Ib621a5af84262430e4c2b00848f102ca3488cfbf Signed-off-by: Laxman Dewangan Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x-generic-dts/+/2884371 Reviewed-by: svcacv GVS: Gerrit_Virtual_Submit --- overlay/tegra234-base-overlay.dtsi | 41 ++++++++++++++++++++++++++++++ tegra234.dtsi | 30 +++++----------------- 2 files changed, 48 insertions(+), 23 deletions(-) diff --git a/overlay/tegra234-base-overlay.dtsi b/overlay/tegra234-base-overlay.dtsi index 411a08a..8688758 100644 --- a/overlay/tegra234-base-overlay.dtsi +++ b/overlay/tegra234-base-overlay.dtsi @@ -344,6 +344,47 @@ iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; }; + i2c@3160000 { + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + }; + + i2c@3180000 { + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + }; + + i2c@3190000 { + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + }; + + i2c@31b0000 { + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + }; + + i2c@31c0000 { + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + }; + + i2c@31e0000 { + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + }; + + i2c@c240000 { + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + }; + + i2c@c250000 { + nvidia,hw-instance-id = <0x7>; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-coherent; + }; + pwm@3280000 { compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; diff --git a/tegra234.dtsi b/tegra234.dtsi index bb3de06..f6af108 100644 --- a/tegra234.dtsi +++ b/tegra234.dtsi @@ -161,10 +161,11 @@ <&bpmp TEGRA234_CLK_APB2APE>; clock-names = "ape", "apb2ape"; power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; + status = "disabled"; + #address-cells = <1>; #size-cells = <1>; ranges = <0x02900000 0x02900000 0x200000>; - status = "disabled"; tegra_ahub: ahub@2900800 { compatible = "nvidia,tegra234-ahub"; @@ -173,10 +174,11 @@ clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + status = "disabled"; + #address-cells = <1>; #size-cells = <1>; ranges = <0x02900800 0x02900800 0x11800>; - status = "disabled"; tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra234-i2s", @@ -441,11 +443,12 @@ compatible = "nvidia,tegra234-ope", "nvidia,tegra210-ope"; reg = <0x2908000 0x100>; + sound-name-prefix = "OPE1"; + status = "disabled"; + #address-cells = <1>; #size-cells = <1>; ranges; - sound-name-prefix = "OPE1"; - status = "disabled"; equalizer@2908100 { compatible = "nvidia,tegra234-peq", @@ -695,8 +698,6 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C1>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 21>, <&gpcdma 21>; dma-names = "rx", "tx"; }; @@ -716,8 +717,6 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C3>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 23>, <&gpcdma 23>; dma-names = "rx", "tx"; }; @@ -737,8 +736,6 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C4>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 26>, <&gpcdma 26>; dma-names = "rx", "tx"; }; @@ -758,8 +755,6 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C6>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 30>, <&gpcdma 30>; dma-names = "rx", "tx"; }; @@ -779,8 +774,6 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C7>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 27>, <&gpcdma 27>; dma-names = "rx", "tx"; }; @@ -807,8 +800,6 @@ clock-names = "div-clk", "parent"; resets = <&bpmp TEGRA234_RESET_I2C9>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 31>, <&gpcdma 31>; dma-names = "rx", "tx"; }; @@ -832,7 +823,6 @@ "nvidia,tegra186-pwm"; reg = <0x3280000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM1>; - clock-names = "pwm"; resets = <&bpmp TEGRA234_RESET_PWM1>; reset-names = "pwm"; status = "disabled"; @@ -1713,8 +1703,6 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C2>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 22>, <&gpcdma 22>; dma-names = "rx", "tx"; }; @@ -1722,7 +1710,6 @@ gen8_i2c: i2c@c250000 { compatible = "nvidia,tegra194-i2c"; reg = <0xc250000 0x100>; - nvidia,hw-instance-id = <0x7>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1735,8 +1722,6 @@ assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; resets = <&bpmp TEGRA234_RESET_I2C8>; reset-names = "i2c"; - iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; - dma-coherent; dmas = <&gpcdma 0>, <&gpcdma 0>; dma-names = "rx", "tx"; }; @@ -3472,4 +3457,3 @@ always-on; }; }; -