From acb70733aad51a36affd0bb35b94f105bf6a3599 Mon Sep 17 00:00:00 2001 From: Gautham Srinivasan Date: Fri, 1 Aug 2025 15:54:03 +0000 Subject: [PATCH] t23x: dts: fix incorrect GPIO port macros Update GPIO port macros to TEGRA234_MAIN_GPIO and TEGRA234_AON_GPIO to reference correct GPIO pin mappings. Bug 5430530 Change-Id: I100f2ddf3fff829805b8bbf88660637bf063d598 Signed-off-by: Gautham Srinivasan Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3422090 Reviewed-by: Hiteshkumar Patel Reviewed-by: Bibek Basu Reviewed-by: svcacv GVS: buildbot_gerritrpt Reviewed-by: Prathamesh Shete --- .../tegra234-p3737-0000+p3701-0000.h | 46 +++++++++---------- .../dt-bindings/tegra234-p3767-0000-common.h | 46 +++++++++---------- 2 files changed, 46 insertions(+), 46 deletions(-) diff --git a/include/platforms/dt-bindings/tegra234-p3737-0000+p3701-0000.h b/include/platforms/dt-bindings/tegra234-p3737-0000+p3701-0000.h index ac710d4..c3e7850 100644 --- a/include/platforms/dt-bindings/tegra234-p3737-0000+p3701-0000.h +++ b/include/platforms/dt-bindings/tegra234-p3737-0000+p3701-0000.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved. + * SPDX-FileCopyrightText: Copyright (c) 2021-2025, NVIDIA CORPORATION. All rights reserved. * * Definitions for Jetson tegra234-p3737-0000-p3701-0000 board. */ @@ -43,25 +43,25 @@ #define HDR40_PIN40 "soc_gpio42_pi0" /* SoC GPIO definitions for 40-pin header */ -#define HDR40_PIN7_GPIO TEGRA_MAIN_GPIO(Q, 6) -#define HDR40_PIN11_GPIO TEGRA_MAIN_GPIO(R, 4) -#define HDR40_PIN12_GPIO TEGRA_MAIN_GPIO(H, 7) -#define HDR40_PIN13_GPIO TEGRA_MAIN_GPIO(R, 0) -#define HDR40_PIN15_GPIO TEGRA_MAIN_GPIO(N, 1) -#define HDR40_PIN16_GPIO TEGRA_AON_GPIO(BB, 0) -#define HDR40_PIN18_GPIO TEGRA_MAIN_GPIO(H, 0) -#define HDR40_PIN19_GPIO TEGRA_MAIN_GPIO(Z, 5) -#define HDR40_PIN21_GPIO TEGRA_MAIN_GPIO(Z, 4) -#define HDR40_PIN22_GPIO TEGRA_MAIN_GPIO(P, 4) -#define HDR40_PIN23_GPIO TEGRA_MAIN_GPIO(Z, 3) -#define HDR40_PIN24_GPIO TEGRA_MAIN_GPIO(Z, 6) -#define HDR40_PIN26_GPIO TEGRA_MAIN_GPIO(Z, 7) -#define HDR40_PIN29_GPIO TEGRA_AON_GPIO(AA, 1) -#define HDR40_PIN31_GPIO TEGRA_AON_GPIO(AA, 0) -#define HDR40_PIN32_GPIO TEGRA_AON_GPIO(BB, 1) -#define HDR40_PIN33_GPIO TEGRA_AON_GPIO(AA, 2) -#define HDR40_PIN35_GPIO TEGRA_MAIN_GPIO(I, 2) -#define HDR40_PIN36_GPIO TEGRA_MAIN_GPIO(R, 5) -#define HDR40_PIN37_GPIO TEGRA_AON_GPIO(AA, 3) -#define HDR40_PIN38_GPIO TEGRA_MAIN_GPIO(I, 1) -#define HDR40_PIN40_GPIO TEGRA_MAIN_GPIO(I, 0) +#define HDR40_PIN7_GPIO TEGRA234_MAIN_GPIO(Q, 6) +#define HDR40_PIN11_GPIO TEGRA234_MAIN_GPIO(R, 4) +#define HDR40_PIN12_GPIO TEGRA234_MAIN_GPIO(H, 7) +#define HDR40_PIN13_GPIO TEGRA234_MAIN_GPIO(R, 0) +#define HDR40_PIN15_GPIO TEGRA234_MAIN_GPIO(N, 1) +#define HDR40_PIN16_GPIO TEGRA234_AON_GPIO(BB, 0) +#define HDR40_PIN18_GPIO TEGRA234_MAIN_GPIO(H, 0) +#define HDR40_PIN19_GPIO TEGRA234_MAIN_GPIO(Z, 5) +#define HDR40_PIN21_GPIO TEGRA234_MAIN_GPIO(Z, 4) +#define HDR40_PIN22_GPIO TEGRA234_MAIN_GPIO(P, 4) +#define HDR40_PIN23_GPIO TEGRA234_MAIN_GPIO(Z, 3) +#define HDR40_PIN24_GPIO TEGRA234_MAIN_GPIO(Z, 6) +#define HDR40_PIN26_GPIO TEGRA234_MAIN_GPIO(Z, 7) +#define HDR40_PIN29_GPIO TEGRA234_AON_GPIO(AA, 1) +#define HDR40_PIN31_GPIO TEGRA234_AON_GPIO(AA, 0) +#define HDR40_PIN32_GPIO TEGRA234_AON_GPIO(BB, 1) +#define HDR40_PIN33_GPIO TEGRA234_AON_GPIO(AA, 2) +#define HDR40_PIN35_GPIO TEGRA234_MAIN_GPIO(I, 2) +#define HDR40_PIN36_GPIO TEGRA234_MAIN_GPIO(R, 5) +#define HDR40_PIN37_GPIO TEGRA234_AON_GPIO(AA, 3) +#define HDR40_PIN38_GPIO TEGRA234_MAIN_GPIO(I, 1) +#define HDR40_PIN40_GPIO TEGRA234_MAIN_GPIO(I, 0) diff --git a/include/platforms/dt-bindings/tegra234-p3767-0000-common.h b/include/platforms/dt-bindings/tegra234-p3767-0000-common.h index 4aa3394..b3610f1 100644 --- a/include/platforms/dt-bindings/tegra234-p3767-0000-common.h +++ b/include/platforms/dt-bindings/tegra234-p3767-0000-common.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. +/* SPDX-FileCopyrightText: Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved. * * Definitions for Jetson tegra234-p3767-0000 board. */ @@ -60,25 +60,25 @@ #define HDR40_PIN40 "soc_gpio42_pi0" /* SoC GPIO definitions for 40-pin header */ -#define HDR40_PIN7_GPIO TEGRA_MAIN_GPIO(AC, 6) -#define HDR40_PIN11_GPIO TEGRA_MAIN_GPIO(R, 4) -#define HDR40_PIN12_GPIO TEGRA_MAIN_GPIO(H, 7) -#define HDR40_PIN13_GPIO TEGRA_MAIN_GPIO(Y, 0) -#define HDR40_PIN15_GPIO TEGRA_MAIN_GPIO(N, 1) -#define HDR40_PIN16_GPIO TEGRA_AON_GPIO(Y, 4) -#define HDR40_PIN18_GPIO TEGRA_MAIN_GPIO(Y, 3) -#define HDR40_PIN19_GPIO TEGRA_MAIN_GPIO(Z, 5) -#define HDR40_PIN21_GPIO TEGRA_MAIN_GPIO(Z, 4) -#define HDR40_PIN22_GPIO TEGRA_MAIN_GPIO(Y, 1) -#define HDR40_PIN23_GPIO TEGRA_MAIN_GPIO(Z, 3) -#define HDR40_PIN24_GPIO TEGRA_MAIN_GPIO(Z, 6) -#define HDR40_PIN26_GPIO TEGRA_MAIN_GPIO(Z, 7) -#define HDR40_PIN29_GPIO TEGRA_AON_GPIO(Q, 5) -#define HDR40_PIN31_GPIO TEGRA_AON_GPIO(Q, 6) -#define HDR40_PIN32_GPIO TEGRA_AON_GPIO(G, 6) -#define HDR40_PIN33_GPIO TEGRA_AON_GPIO(H, 0) -#define HDR40_PIN35_GPIO TEGRA_MAIN_GPIO(I, 2) -#define HDR40_PIN36_GPIO TEGRA_MAIN_GPIO(R, 5) -#define HDR40_PIN37_GPIO TEGRA_AON_GPIO(Y, 2) -#define HDR40_PIN38_GPIO TEGRA_MAIN_GPIO(I, 1) -#define HDR40_PIN40_GPIO TEGRA_MAIN_GPIO(I, 0) +#define HDR40_PIN7_GPIO TEGRA234_MAIN_GPIO(AC, 6) +#define HDR40_PIN11_GPIO TEGRA234_MAIN_GPIO(R, 4) +#define HDR40_PIN12_GPIO TEGRA234_MAIN_GPIO(H, 7) +#define HDR40_PIN13_GPIO TEGRA234_MAIN_GPIO(Y, 0) +#define HDR40_PIN15_GPIO TEGRA234_MAIN_GPIO(N, 1) +#define HDR40_PIN16_GPIO TEGRA234_AON_GPIO(Y, 4) +#define HDR40_PIN18_GPIO TEGRA234_MAIN_GPIO(Y, 3) +#define HDR40_PIN19_GPIO TEGRA234_MAIN_GPIO(Z, 5) +#define HDR40_PIN21_GPIO TEGRA234_MAIN_GPIO(Z, 4) +#define HDR40_PIN22_GPIO TEGRA234_MAIN_GPIO(Y, 1) +#define HDR40_PIN23_GPIO TEGRA234_MAIN_GPIO(Z, 3) +#define HDR40_PIN24_GPIO TEGRA234_MAIN_GPIO(Z, 6) +#define HDR40_PIN26_GPIO TEGRA234_MAIN_GPIO(Z, 7) +#define HDR40_PIN29_GPIO TEGRA234_AON_GPIO(Q, 5) +#define HDR40_PIN31_GPIO TEGRA234_AON_GPIO(Q, 6) +#define HDR40_PIN32_GPIO TEGRA234_AON_GPIO(G, 6) +#define HDR40_PIN33_GPIO TEGRA234_AON_GPIO(H, 0) +#define HDR40_PIN35_GPIO TEGRA234_MAIN_GPIO(I, 2) +#define HDR40_PIN36_GPIO TEGRA234_MAIN_GPIO(R, 5) +#define HDR40_PIN37_GPIO TEGRA234_AON_GPIO(Y, 2) +#define HDR40_PIN38_GPIO TEGRA234_MAIN_GPIO(I, 1) +#define HDR40_PIN40_GPIO TEGRA234_MAIN_GPIO(I, 0)