From b1f3a07be229c3e73bfc9d1d43fd2bf7166189dd Mon Sep 17 00:00:00 2001
From: Asha T <atalambedu@nvidia.com>
Date: Fri, 17 Mar 2023 14:46:07 +0530
Subject: [PATCH] p3768: Added missing hdr40 pin config

Current hdr40 dtsi misses the extperiph clks
and pwm pins configuration. Hence added the same
through this CL

Bug 4033331

Change-Id: I39b2b54bbe1057dfee73451bb98e7faefd32ec9d
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/platform/t23x/p3768-dts/+/2872809
(cherry picked from commit 572941f05417513d55b8e120b2f819e72cec127e)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/platform/t23x/p3768-dts/+/2872805
(cherry picked from commit ba24d22a526ced00a0511aed2d425ffdfa986f04)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/platform/t23x/p3768-dts/+/2889623
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Asha Talambedu <atalambedu@nvidia.com>
Tested-by: Asha Talambedu <atalambedu@nvidia.com>
---
 overlay/tegra234-p3767-0000-common-hdr40.dtsi | 41 +++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/overlay/tegra234-p3767-0000-common-hdr40.dtsi b/overlay/tegra234-p3767-0000-common-hdr40.dtsi
index 2dd28d6..a4406bd 100644
--- a/overlay/tegra234-p3767-0000-common-hdr40.dtsi
+++ b/overlay/tegra234-p3767-0000-common-hdr40.dtsi
@@ -61,6 +61,13 @@
 					nvidia,tristate = <TEGRA_PIN_DISABLE>;
 					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
+				hdr40-pin15 {
+					nvidia,pins = "soc_gpio39_pn1";
+					nvidia,function = "gp";
+					nvidia,pin-group = "pwm1";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
 				hdr40-pin16 {
 					nvidia,pins = "spi3_cs0_py3";
 					nvidia,function = "spi3";
@@ -123,6 +130,40 @@
 				hdr40-pin28 {
 					nvidia,pins = "gen2_i2c_scl_pcc7";
 				};
+				hdr40-pin29 {
+					nvidia,pins = "soc_gpio32_pq5";
+					nvidia,function = "extperiph3";
+					nvidia,pin-group = "extperiph3_clk";
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+					nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+					nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+				};
+				hdr40-pin31 {
+					nvidia,pins = "soc_gpio33_pq6";
+					nvidia,function = "extperiph4";
+					nvidia,pin-group = "extperiph4_clk";
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+					nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+					nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+				};
+				hdr40-pin32 {
+					nvidia,pins = "soc_gpio19_pg6";
+					nvidia,function = "gp";
+					nvidia,pin-group = "pwm7";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
+				hdr40-pin33 {
+					nvidia,pins = "soc_gpio21_ph0";
+					nvidia,function = "gp";
+					nvidia,pin-group = "pwm5";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+				};
 				hdr40-pin35 {
 					nvidia,pins = "soc_gpio44_pi2";
 					nvidia,function = "i2s2";