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base: tegra234: Bump #address-cells and #size-cells

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The #address-cells and #size-cells properties for the top-level bus were
set to 1 because that was enough to represent the register ranges of all
the IP blocks on that bus. However, most of these devices can do DMA to
a larger address space, so translation of DMA addresses needs to happen
in a 64-bit address space.

Partially this was already done by the memory controller increasing that
address space by setting #address-cells and #size-cells to 2, but a full
DMA address translation would still cause truncation when traversing to
the top-level bus.

Fix this by setting #address-cells = <2> and #size-cells = <2> on the
top-level bus and adjusting all "reg" and "ranges" properties of its
children.

While at it, also move the PCI and GPU nodes back under the top-level
bus where they belong. The were put outside of it to work around this
same problem.

This change is based on the below change from mainline v6.3-rc5:
     commit 2838cfddbc1c4e12dacf8219efb481ab11c114a4

Bug 4057304

Change-Id: Iedd79836dac2a6760a604da6e61db4735e246435
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x-generic-dts/+/2884732
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Laxman Dewangan
2023-04-08 17:03:01 +00:00
parent 6b3e58d9f5
commit ddedbadb95
4 changed files with 1082 additions and 1087 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
overlay/tegra234-base-overlay.dtsi
View File

@@ -41,6 +41,7 @@
qspi0 = "/bus@0/spi@3270000";
};
bus@0 {
pcie@140a0000 {
iommus = <&smmu_niso1 TEGRA234_SID_PCIE8>;
};
@@ -101,7 +102,6 @@
iommus = <&smmu_niso1 TEGRA234_SID_PCIE10>;
};
bus@0 {
hda@3510000 {
iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
};
@@ -330,9 +330,9 @@
ethernet@2310000 {
compatible = "nvidia,nveqos";
reg = <0x02310000 0x10000>, /* EQOS Base Register */
<0x023D0000 0x10000>, /* MACSEC Base Register */
<0x02300000 0x10000>; /* HV Base Register */
reg = <0x0 0x02310000 0x0 0x10000>, /* EQOS Base Register */
<0x0 0x023D0000 0x0 0x10000>, /* MACSEC Base Register */
<0x0 0x02300000 0x0 0x10000>; /* HV Base Register */
reg-names = "mac", "macsec-base", "hypervisor";
interrupts = <0 194 0x4>, /* common */
<0 186 0x4>, /* vm0 */
@@ -407,10 +407,10 @@
ethernet@6800000 {
compatible = "nvidia,tegra234-mgbe";
reg = <0x06810000 0x10000>, /* MGBE base */
<0x068A0000 0x10000>, /* XPCS base */
<0x068D0000 0x10000>, /* MACsec RM base */
<0x06800000 0x10000>; /* HV base */
reg = <0x0 0x06810000 0x0 0x10000>, /* MGBE base */
<0x0 0x068A0000 0x0 0x10000>, /* XPCS base */
<0x0 0x068D0000 0x0 0x10000>, /* MACsec RM base */
<0x0 0x06800000 0x0 0x10000>; /* HV base */
reg-names = "mac", "xpcs", "macsec-base", "hypervisor";
interrupts = <0 384 0x4>, /* common */
<0 385 0x4>, /* vm0 */
@@ -477,13 +477,10 @@
};
host1x@13e00000 {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges = <0x14800000 0x14800000 0x02000000>,
<0x24700000 0x24700000 0x00080000>;
ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>,
<0x0 0x24700000 0x0 0x24700000 0x0 0x00080000>;
};
spi@3270000 {

2
overlay/tegra234-camera.dtsi
View File

@@ -225,7 +225,7 @@
isp: isp@14800000 {
compatible = "nvidia,tegra194-isp";
reg = <0x14800000 0x00010000>;
reg = <0x0 0x14800000 0x0 0x00010000>;
resets = <&bpmp TEGRA234_RESET_ISP>;
reset-names = "isp";

200
overlay/tegra234-soc-overlay.dtsi
View File

@@ -21,9 +21,9 @@
bus@0 {
watchdog@2190000 {
compatible = "nvidia,tegra-wdt-t234";
reg = <0x02190000 0x10000>, /* WDT0 */
<0x02090000 0x10000>, /* TMR0 */
<0x02080000 0x10000>; /* TKE */
reg = <0x0 0x02190000 0x0 0x10000>, /* WDT0 */
<0x0 0x02090000 0x0 0x10000>, /* TMR0 */
<0x0 0x02080000 0x0 0x10000>; /* TKE */
interrupts = <0 7 0x4 0 8 0x4>; /* TKE shared int */
nvidia,watchdog-index = <0>;
nvidia,timer-index = <7>;
@@ -36,8 +36,8 @@
pinmux: tegra_pinctrl: pinmux@2430000 {
compatible = "nvidia,tegra234-pinmux";
reg = <0x2430000 0x19100>,
<0xc300000 0x4000>;
reg = <0x0 0x2430000 0x0 0x19100>,
<0x0 0xc300000 0x0 0x4000>;
#gpio-range-cells = <3>;
status = "disabled";
eqos_mii_rx_input_state_disable: eqos_rx_disable {
@@ -60,12 +60,12 @@
tegra_ufs: ufshci@2500000 {
compatible = "tegra234,ufs_variant";
reg = <0x02500000 0x4000>,
<0x02510000 0x1000>,
<0x02518000 0x1000>,
<0x02520000 0x1000>,
<0x02470000 0x4000>,
<0x02480000 0x4000>;
reg = <0x0 0x02500000 0x0 0x4000>,
<0x0 0x02510000 0x0 0x1000>,
<0x0 0x02518000 0x0 0x1000>,
<0x0 0x02520000 0x0 0x1000>,
<0x0 0x02470000 0x0 0x4000>,
<0x0 0x02480000 0x0 0x4000>;
interrupts = < 0 44 0x04 >;
interconnects = <&mc TEGRA234_MEMORY_CLIENT_UFSHCR>,
<&mc TEGRA234_MEMORY_CLIENT_UFSHCW>;
@@ -142,7 +142,7 @@
serial@3110000 {
compatible = "nvidia,tegra194-hsuart";
reg = <0x03110000 0x10000>;
reg = <0x0 0x03110000 0x0 0x10000>;
reg-shift = <2>;
interrupts = <0 113 0x04>;
clocks = <&bpmp TEGRA234_CLK_UARTB>,
@@ -155,7 +155,7 @@
tachometer@39c0000 {
compatible = "nvidia,pwm-tegra234-tachometer";
reg = <0x039c0000 0x10>;
reg = <0x0 0x039c0000 0x0 0x10>;
#pwm-cells = <2>;
clocks = <&bpmp TEGRA234_CLK_TACH0>;
clock-names = "tach";
@@ -169,9 +169,9 @@
gpu@17000000 {
compatible = "nvidia,ga10b";
reg = <0x17000000 0x01000000>,
<0x18000000 0x01000000>,
<0x03b41000 0x00001000>;
reg = <0x0 0x17000000 0x0 0x01000000>,
<0x0 0x18000000 0x0 0x01000000>,
<0x0 0x03b41000 0x0 0x00001000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
@@ -198,7 +198,7 @@
status = "disabled";
compatible = "nvidia,tegra186-arad-oot";
reg = <0x290e400 0x400>;
reg = <0x0 0x290e400 0x0 0x400>;
#address-cells = <1>;
#size-cells = <1>;
#sound-dai-cells = <1>;
@@ -209,7 +209,7 @@
compatible = "nvidia,tegra234-afc-oot",
"nvidia,tegra186-afc-oot";
reg = <0x2907000 0x100>;
reg = <0x0 0x2907000 0x0 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC1";
@@ -221,7 +221,7 @@
compatible = "nvidia,tegra234-afc-oot",
"nvidia,tegra186-afc-oot";
reg = <0x2907100 0x100>;
reg = <0x0 0x2907100 0x0 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC2";
@@ -233,7 +233,7 @@
compatible = "nvidia,tegra234-afc-oot",
"nvidia,tegra186-afc-oot";
reg = <0x2907200 0x100>;
reg = <0x0 0x2907200 0x0 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC3";
@@ -245,7 +245,7 @@
compatible = "nvidia,tegra234-afc-oot",
"nvidia,tegra186-afc-oot";
reg = <0x2907300 0x100>;
reg = <0x0 0x2907300 0x0 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC4";
@@ -257,7 +257,7 @@
compatible = "nvidia,tegra234-afc-oot",
"nvidia,tegra186-afc-oot";
reg = <0x2907400 0x100>;
reg = <0x0 0x2907400 0x0 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC5";
@@ -269,7 +269,7 @@
compatible = "nvidia,tegra234-afc-oot",
"nvidia,tegra186-afc-oot";
reg = <0x2907500 0x100>;
reg = <0x0 0x2907500 0x0 0x100>;
#address-cells = <1>;
#size-cells = <1>;
sound-name-prefix = "AFC6";
@@ -281,10 +281,10 @@
host1x@13e00000 {
dma-coherent;
reg = <0x13e00000 0x10000>,
<0x13e10000 0x10000>,
<0x13e40000 0x10000>,
<0x13ef0000 0x60000>;
reg = <0x0 0x13e00000 0x0 0x10000>,
<0x0 0x13e10000 0x0 0x10000>,
<0x0 0x13e40000 0x0 0x10000>,
<0x0 0x13ef0000 0x0 0x60000>;
reg-names = "common", "hypervisor", "vm", "actmon";
clocks = <&bpmp TEGRA234_CLK_HOST1X>,
<&bpmp TEGRA234_CLK_ACTMON>;
@@ -292,7 +292,7 @@
nvjpg@15380000 {
compatible = "nvidia,tegra234-nvjpg";
reg = <0x15380000 0x00040000>;
reg = <0x0 0x15380000 0x0 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_NVJPG>;
clock-names = "nvjpg";
resets = <&bpmp TEGRA234_RESET_NVJPG>;
@@ -311,7 +311,7 @@
nvenc@154c0000 {
compatible = "nvidia,tegra234-nvenc";
reg = <0x154c0000 0x00040000>;
reg = <0x0 0x154c0000 0x0 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_NVENC>;
clock-names = "nvenc";
resets = <&bpmp TEGRA234_RESET_NVENC>;
@@ -328,7 +328,7 @@
nvjpg@15540000 {
compatible = "nvidia,tegra234-nvjpg";
reg = <0x15540000 0x00040000>;
reg = <0x0 0x15540000 0x0 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_NVJPG1>;
clock-names = "nvjpg";
resets = <&bpmp TEGRA234_RESET_NVJPG1>;
@@ -347,7 +347,7 @@
ofa@15a50000 {
compatible = "nvidia,tegra234-ofa";
reg = <0x15a50000 0x00040000>;
reg = <0x0 0x15a50000 0x0 0x00040000>;
clocks = <&bpmp TEGRA234_CLK_OFA>;
clock-names = "ofa";
resets = <&bpmp TEGRA234_RESET_OFA>;
@@ -364,7 +364,7 @@
se@15810000 {
compatible = "nvidia,tegra234-se1-nvhost";
reg = <0x15810000 0x10000>;
reg = <0x0 0x15810000 0x0 0x10000>;
supported-algos = "drbg";
nvidia,io-coherent;
opcode_addr = <0x1004>;
@@ -381,7 +381,7 @@
se@15820000 {
compatible = "nvidia,tegra234-se2-nvhost";
reg = <0x15820000 0x10000>;
reg = <0x0 0x15820000 0x0 0x10000>;
supported-algos = "aes", "cmac", "xts", "aead";
nvidia,io-coherent;
opcode_addr = <0x2004>;
@@ -399,7 +399,7 @@
se@15840000 {
compatible = "nvidia,tegra234-se4-nvhost";
reg = <0x15840000 0x10000>;
reg = <0x0 0x15840000 0x0 0x10000>;
supported-algos = "sha", "sha3", "hmac";
nvidia,io-coherent;
opcode_addr = <0x4004>;
@@ -417,7 +417,7 @@
tsec@15500000 {
compatible = "nvidia,tegra234-tsec";
reg = <0x15500000 0x00040000>;
reg = <0x0 0x15500000 0x0 0x00040000>;
interrupts = <0 228 0x04>;
resets = <&bpmp TEGRA234_RESET_TSEC>;
clocks = <&bpmp TEGRA234_CLK_TSEC>,
@@ -434,60 +434,60 @@
tegra_soc_hwpm {
compatible = "nvidia,t234-soc-hwpm";
dma-coherent;
reg = <0xf100000 0x1000>,
<0xf101000 0x1000>,
<0xf102000 0x1000>,
<0xf103000 0x1000>,
<0xf104000 0x1000>,
<0xf105000 0x1000>,
<0xf106000 0x1000>,
<0xf107000 0x1000>,
<0xf108000 0x1000>,
<0xf109000 0x1000>,
<0xf10a000 0x1000>,
<0xf10b000 0x1000>,
<0xf10c000 0x1000>,
<0xf10d000 0x1000>,
<0xf10e000 0x1000>,
<0xf10f000 0x1000>,
<0xf110000 0x1000>,
<0xf111000 0x1000>,
<0xf112000 0x1000>,
<0xf113000 0x1000>,
<0xf114000 0x1000>,
<0xf115000 0x1000>,
<0xf116000 0x1000>,
<0xf117000 0x1000>,
<0xf118000 0x1000>,
<0xf119000 0x1000>,
<0xf11a000 0x1000>,
<0xf11b000 0x1000>,
<0xf11c000 0x1000>,
<0xf11d000 0x1000>,
<0xf11e000 0x1000>,
<0xf11f000 0x1000>,
<0xf120000 0x1000>,
<0xf121000 0x1000>,
<0xf122000 0x1000>,
<0xf123000 0x1000>,
<0xf124000 0x1000>,
<0xf125000 0x1000>,
<0xf126000 0x1000>,
<0xf127000 0x1000>,
<0xf128000 0x1000>,
<0xf129000 0x1000>,
<0xf12a000 0x1000>,
<0xf12b000 0x1000>,
<0xf12c000 0x1000>,
<0xf12d000 0x1000>,
<0xf12e000 0x1000>,
<0xf12f000 0x1000>,
<0xf130000 0x1000>,
<0xf131000 0x1000>,
<0xf132000 0x1000>,
<0xf133000 0x1000>,
<0xf14a000 0x2000>,
<0xf14d000 0x1000>;
reg = <0x0 0xf100000 0x0 0x1000>,
<0x0 0xf101000 0x0 0x1000>,
<0x0 0xf102000 0x0 0x1000>,
<0x0 0xf103000 0x0 0x1000>,
<0x0 0xf104000 0x0 0x1000>,
<0x0 0xf105000 0x0 0x1000>,
<0x0 0xf106000 0x0 0x1000>,
<0x0 0xf107000 0x0 0x1000>,
<0x0 0xf108000 0x0 0x1000>,
<0x0 0xf109000 0x0 0x1000>,
<0x0 0xf10a000 0x0 0x1000>,
<0x0 0xf10b000 0x0 0x1000>,
<0x0 0xf10c000 0x0 0x1000>,
<0x0 0xf10d000 0x0 0x1000>,
<0x0 0xf10e000 0x0 0x1000>,
<0x0 0xf10f000 0x0 0x1000>,
<0x0 0xf110000 0x0 0x1000>,
<0x0 0xf111000 0x0 0x1000>,
<0x0 0xf112000 0x0 0x1000>,
<0x0 0xf113000 0x0 0x1000>,
<0x0 0xf114000 0x0 0x1000>,
<0x0 0xf115000 0x0 0x1000>,
<0x0 0xf116000 0x0 0x1000>,
<0x0 0xf117000 0x0 0x1000>,
<0x0 0xf118000 0x0 0x1000>,
<0x0 0xf119000 0x0 0x1000>,
<0x0 0xf11a000 0x0 0x1000>,
<0x0 0xf11b000 0x0 0x1000>,
<0x0 0xf11c000 0x0 0x1000>,
<0x0 0xf11d000 0x0 0x1000>,
<0x0 0xf11e000 0x0 0x1000>,
<0x0 0xf11f000 0x0 0x1000>,
<0x0 0xf120000 0x0 0x1000>,
<0x0 0xf121000 0x0 0x1000>,
<0x0 0xf122000 0x0 0x1000>,
<0x0 0xf123000 0x0 0x1000>,
<0x0 0xf124000 0x0 0x1000>,
<0x0 0xf125000 0x0 0x1000>,
<0x0 0xf126000 0x0 0x1000>,
<0x0 0xf127000 0x0 0x1000>,
<0x0 0xf128000 0x0 0x1000>,
<0x0 0xf129000 0x0 0x1000>,
<0x0 0xf12a000 0x0 0x1000>,
<0x0 0xf12b000 0x0 0x1000>,
<0x0 0xf12c000 0x0 0x1000>,
<0x0 0xf12d000 0x0 0x1000>,
<0x0 0xf12e000 0x0 0x1000>,
<0x0 0xf12f000 0x0 0x1000>,
<0x0 0xf130000 0x0 0x1000>,
<0x0 0xf131000 0x0 0x1000>,
<0x0 0xf132000 0x0 0x1000>,
<0x0 0xf133000 0x0 0x1000>,
<0x0 0xf14a000 0x0 0x2000>,
<0x0 0xf14d000 0x0 0x1000>;
reg-names = "perfmon_vi0",
"perfmon_vi1",
@@ -542,7 +542,7 @@
nvdla0: nvdla0@15880000 {
compatible = "nvidia,tegra234-nvdla";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAA>;
reg = <0x15880000 0x00040000>;
reg = <0x0 0x15880000 0x0 0x00040000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
resets = <&bpmp TEGRA234_RESET_DLA0>;
@@ -563,7 +563,7 @@
nvdla1: nvdla1@158c0000 {
compatible = "nvidia,tegra234-nvdla";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAB>;
reg = <0x158c0000 0x00040000>;
reg = <0x0 0x158c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
resets = <&bpmp TEGRA234_RESET_DLA1>;
@@ -584,8 +584,8 @@
pva0: pva0@16000000 {
compatible = "nvidia,tegra234-pva";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PVA>;
reg = <0x16000000 0x800000>,
<0x24700000 0x080000>;
reg = <0x0 0x16000000 0x0 0x800000>,
<0x0 0x24700000 0x0 0x080000>;
interrupts = <0 234 0x04>,
<0 432 0x04>,
<0 433 0x04>,
@@ -665,9 +665,9 @@
mttcan@c310000 {
compatible = "nvidia,tegra194-mttcan";
reg = <0x0c310000 0x144>,
<0x0c311000 0x32>,
<0x0c312000 0x1000>;
reg = <0x0 0x0c310000 0x0 0x144>,
<0x0 0x0c311000 0x0 0x32>,
<0x0 0x0c312000 0x0 0x1000>;
reg-names = "can-regs", "glue-regs", "msg-ram";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
pll_source = "pllaon";
@@ -695,9 +695,9 @@
mttcan@c320000 {
compatible = "nvidia,tegra194-mttcan";
reg = <0x0c320000 0x144>,
<0x0c321000 0x32>,
<0x0c322000 0x1000>;
reg = <0x0 0x0c320000 0x0 0x144>,
<0x0 0x0c321000 0x0 0x32>,
<0x0 0x0c322000 0x0 0x1000>;
reg-names = "can-regs", "glue-regs", "msg-ram";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pll_source = "pllaon";
@@ -725,7 +725,7 @@
hsp_top2: hsp@1600000 {
compatible = "nvidia,tegra234-hsp";
reg = <0x1600000 0x90000>;
reg = <0x0 0x1600000 0x0 0x90000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "shared0";
#mbox-cells = <2>;

358
tegra234.dtsi
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