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tegra234: Move dma-coherant property from overlay to base

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The base DTSI file of tegra234, tegra234.dtsi, have already
property of dma-coherent inside node host1x@13e00000 in mainline.

Move this property from overlay to the base file to match
tegra234.dtsi with mainline.

Bug 4037899

Change-Id: I1260ce822a594308e9a0cc672c4669d185e20277
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2940603
(cherry picked from commit 5fd589841f)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2955398
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Laxman Dewangan
2023-07-21 15:25:44 +00:00
committed by mobile promotions
parent e01cba0fe5
commit e177fde95a
2 changed files with 1 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
overlay/tegra234-soc-overlay.dtsi
View File

@@ -521,8 +521,6 @@
assigned-clocks = <&bpmp TEGRA234_CLK_HOST1X>; assigned-clocks = <&bpmp TEGRA234_CLK_HOST1X>;
assigned-clock-rates = <204000000>; assigned-clock-rates = <204000000>;
dma-coherent;
reg = <0x0 0x13e00000 0x0 0x10000>, reg = <0x0 0x13e00000 0x0 0x10000>,
<0x0 0x13e10000 0x0 0x10000>, <0x0 0x13e10000 0x0 0x10000>,
<0x0 0x13e40000 0x0 0x10000>, <0x0 0x13e40000 0x0 0x10000>,

1
tegra234.dtsi
View File

@@ -2150,6 +2150,7 @@
interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem"; interconnect-names = "dma-mem";
iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
dma-coherent;
/* Context isolation domains */ /* Context isolation domains */
iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,