From f41d403b25f4fe55a8d0d2ac6d3b3a1b2578e3bc Mon Sep 17 00:00:00 2001
From: Vedant Deshpande <vedantd@nvidia.com>
Date: Fri, 16 Aug 2024 18:43:48 +0000
Subject: [PATCH] arm64: tegra: Add p3767 PCIe C4 EP details

Add implementation details for Orin NX/Nano PCIe EP on C4.

Signed-off-by: Vedant Deshpande <vedantd@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Bug 4707773

Change-Id: Ie64897c6772ab00efc5099fa69e4a75eb78463df
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3207080
(cherry picked from commit fae586695fb2b83bb370ecdd80d1da1289920f52)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3216031
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
 tegra234-p3768-0000+p3767.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/tegra234-p3768-0000+p3767.dtsi b/tegra234-p3768-0000+p3767.dtsi
index 81d4f4f..19340d1 100644
--- a/tegra234-p3768-0000+p3767.dtsi
+++ b/tegra234-p3768-0000+p3767.dtsi
@@ -186,6 +186,18 @@
 			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
 		};
 
+		pcie-ep@14160000 {/* C4 - End Point */
+			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+					<&p2u_hsio_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+			reset-gpios = <&gpio
+					TEGRA234_MAIN_GPIO(L, 1)
+					GPIO_ACTIVE_LOW>;
+			nvidia,refclk-select-gpios = <&gpio_aon
+							TEGRA234_AON_GPIO(AA, 4)
+							GPIO_ACTIVE_HIGH>;
+		};
+
 		/* C7 - M.2 Key-M */
 		pcie@141e0000 {
 			status = "okay";