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tegra234: Move reset/clock names property to overlay

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The serial and qspi nodes of mainline version of tegra234.dtsi
do not have the clock and reset names as properties.

Match the tegra234.dtsi and move these properties to overlay.

Bug 4037899

Change-Id: I47647ece2d99430623bbaf7af5176298405c277a
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2945386
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Laxman Dewangan
2023-07-31 12:46:26 +00:00
committed by mobile promotions
parent fb6e6b2f31
commit f596618d50
2 changed files with 12 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
overlay/tegra234-base-overlay.dtsi
View File

@@ -428,11 +428,16 @@
}; };
spi@3270000 { spi@3270000 {
reset-names = "qspi";
dma-names = "rx", "tx"; dma-names = "rx", "tx";
dma-coherent; dma-coherent;
iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>;
}; };
spi@3300000 {
reset-names = "qspi";
};
i2c@3160000 { i2c@3160000 {
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dma-coherent; dma-coherent;
@@ -655,6 +660,11 @@
cap-sd-highspeed; cap-sd-highspeed;
cap-mmc-highspeed; cap-mmc-highspeed;
}; };
serial@3100000 {
clock-names = "serial";
reset-names = "serial";
};
}; };
cpus { cpus {

6
tegra234.dtsi
View File

@@ -682,9 +682,7 @@
reg = <0x0 0x03100000 0x0 0x10000>; reg = <0x0 0x03100000 0x0 0x10000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_UARTA>; clocks = <&bpmp TEGRA234_CLK_UARTA>;
clock-names = "serial";
resets = <&bpmp TEGRA234_RESET_UARTA>; resets = <&bpmp TEGRA234_RESET_UARTA>;
reset-names = "serial";
status = "disabled"; status = "disabled";
}; };
@@ -819,7 +817,6 @@
<&bpmp TEGRA234_CLK_QSPI0_PM>; <&bpmp TEGRA234_CLK_QSPI0_PM>;
clock-names = "qspi", "qspi_out"; clock-names = "qspi", "qspi_out";
resets = <&bpmp TEGRA234_RESET_QSPI0>; resets = <&bpmp TEGRA234_RESET_QSPI0>;
reset-names = "qspi";
status = "disabled"; status = "disabled";
}; };
@@ -903,7 +900,6 @@
<&bpmp TEGRA234_CLK_QSPI1_PM>; <&bpmp TEGRA234_CLK_QSPI1_PM>;
clock-names = "qspi", "qspi_out"; clock-names = "qspi", "qspi_out";
resets = <&bpmp TEGRA234_RESET_QSPI1>; resets = <&bpmp TEGRA234_RESET_QSPI1>;
reset-names = "qspi";
status = "disabled"; status = "disabled";
}; };
@@ -2973,9 +2969,11 @@
sram@40000000 { sram@40000000 {
compatible = "nvidia,tegra234-sysram", "mmio-sram"; compatible = "nvidia,tegra234-sysram", "mmio-sram";
reg = <0x0 0x40000000 0x0 0x80000>; reg = <0x0 0x40000000 0x0 0x80000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x0 0x40000000 0x80000>; ranges = <0x0 0x0 0x40000000 0x80000>;
no-memory-wc; no-memory-wc;
cpu_bpmp_tx: sram@70000 { cpu_bpmp_tx: sram@70000 {