From fb6e6b2f313691fa1a3a7c1f4eed113ecfc078a8 Mon Sep 17 00:00:00 2001
From: Laxman Dewangan <ldewangan@nvidia.com>
Date: Mon, 31 Jul 2023 10:59:07 +0000
Subject: [PATCH] tegra234: Move un-upstreamed pci nodes to overlay

PCIE nodes get added in the base DTS file
"tegra234-p3768-0000+p3767-0000" which are not up-streamed
to mainline yet. Move such nodes to the overlay file.

Bug 4037899

Change-Id: I3b58e9d6a118ab399fd4dad512b51ea59e1aa443
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2945336
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
---
 overlay/tegra234-p3768-0000+p3767-0000.dts | 44 ++++++++++++++++++++++
 tegra234-p3768-0000+p3767-0000.dts         | 44 ----------------------
 2 files changed, 44 insertions(+), 44 deletions(-)

diff --git a/overlay/tegra234-p3768-0000+p3767-0000.dts b/overlay/tegra234-p3768-0000+p3767-0000.dts
index 57e5810..969e5b4 100644
--- a/overlay/tegra234-p3768-0000+p3767-0000.dts
+++ b/overlay/tegra234-p3768-0000+p3767-0000.dts
@@ -109,6 +109,50 @@
 					};
 				};
 
+				/* C1 - M.2 Key-E */
+				pcie@14100000 {
+					status = "okay";
+
+					vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+
+					phys = <&p2u_hsio_3>;
+					phy-names = "p2u-0";
+				};
+
+				/* C4 - M.2 Key-M */
+				pcie@14160000 {
+					status = "okay";
+
+					vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+
+					phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+					       <&p2u_hsio_7>;
+					phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+				};
+
+				/* C8 - Ethernet */
+				pcie@140a0000 {
+					status = "okay";
+
+					num-lanes = <2>;
+
+					phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
+					phy-names = "p2u-0", "p2u-1";
+
+					vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+					vpcie3v3-supply = <&vdd_3v3_pcie>;
+				};
+
+				/* C7 - M.2 Key-M */
+				pcie@141e0000 {
+					status = "okay";
+
+					vddio-pex-ctl-supply = <&vdd_1v8_ao>;
+
+					phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
+					phy-names = "p2u-0", "p2u-1";
+				};
+
 				/* PWM1, 40pin header, pin 15 */
 				pwm@3280000 {
 					status = "okay";
diff --git a/tegra234-p3768-0000+p3767-0000.dts b/tegra234-p3768-0000+p3767-0000.dts
index cadb249..32eb95d 100644
--- a/tegra234-p3768-0000+p3767-0000.dts
+++ b/tegra234-p3768-0000+p3767-0000.dts
@@ -39,50 +39,6 @@
 		padctl@3520000 {
 			status = "okay";
 		};
-
-		/* C1 - M.2 Key-E */
-		pcie@14100000 {
-			status = "okay";
-
-			vddio-pex-ctl-supply = <&vdd_1v8_ao>;
-
-			phys = <&p2u_hsio_3>;
-			phy-names = "p2u-0";
-		};
-
-		/* C4 - M.2 Key-M */
-		pcie@14160000 {
-			status = "okay";
-
-			vddio-pex-ctl-supply = <&vdd_1v8_ao>;
-
-			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
-			       <&p2u_hsio_7>;
-			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
-		};
-
-		/* C8 - Ethernet */
-		pcie@140a0000 {
-			status = "okay";
-
-			num-lanes = <2>;
-
-			phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
-			phy-names = "p2u-0", "p2u-1";
-
-			vddio-pex-ctl-supply = <&vdd_1v8_ao>;
-			vpcie3v3-supply = <&vdd_3v3_pcie>;
-		};
-
-		/* C7 - M.2 Key-M */
-		pcie@141e0000 {
-			status = "okay";
-
-			vddio-pex-ctl-supply = <&vdd_1v8_ao>;
-
-			phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
-			phy-names = "p2u-0", "p2u-1";
-		};
 	};
 
 	gpio-keys {