From fb7d1ce43e6c2089486c16938456c28e896768c7 Mon Sep 17 00:00:00 2001
From: Gautham Srinivasan <gauthams@nvidia.com>
Date: Wed, 8 Nov 2023 02:35:22 +0000
Subject: [PATCH] nv-soc: Add PCIe C4 EP DTS node

Add PCIe C4 EP controller definition in device tree for T234 devices

Bug 4076164
Bug 4052872

Change-Id: I5fc4755c2105bc7c7cae4c41b7404002b2a60458
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3012402
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
---
 nv-soc/tegra234-soc-overlay.dtsi | 46 ++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/nv-soc/tegra234-soc-overlay.dtsi b/nv-soc/tegra234-soc-overlay.dtsi
index 31bb509..e3f284d 100644
--- a/nv-soc/tegra234-soc-overlay.dtsi
+++ b/nv-soc/tegra234-soc-overlay.dtsi
@@ -132,6 +132,17 @@
 		};
 
 		pinmux@2430000 {
+			pex_rst_c4_in_state: pex_rst_c4_in {
+				pex_rst {
+					nvidia,pins = "pex_l4_rst_n_pl1";
+					nvidia,function = "rsvd1";
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+					nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+				};
+			};
+
 			eqos_mii_rx_input_state_disable: eqos_rx_disable {
 				eqos {
 					nvidia,pins = "eqos_rd0_pe6","eqos_rd1_pe7",
@@ -883,6 +894,41 @@
 			status = "disabled";
 		};
 
+		pcie-ep@14160000 {
+			compatible = "nvidia,tegra234-pcie-ep";
+			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
+			reg = <0x00 0x14160000 0x0 0x00020000     /* appl registers (128K)      */
+				0x00 0x36040000 0x0 0x00040000    /* iATU_DMA reg space (256K)  */
+				0x00 0x36080000 0x0 0x00040000    /* DBI space (256K)           */
+				0x21 0x40000000 0x3 0x00000000>;  /* Address Space (12G)        */
+			reg-names = "appl", "atu_dma", "dbi", "addr_space";
+			num-lanes = <4>;
+			clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
+			clock-names = "core";
+			resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
+			       <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
+			reset-names = "apb", "core";
+
+			pinctrl-names = "default";
+			pinctrl-0 = <&pex_rst_c4_in_state>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
+			interrupt-names = "intr";
+			nvidia,bpmp = <&bpmp 4>;
+			nvidia,enable-ext-refclk;
+			nvidia,aspm-cmrt-us = <60>;
+			nvidia,aspm-pwr-on-t-us = <20>;
+			nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+			num-ib-windows = <2>;
+			num-ob-windows = <8>;
+			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
+				      <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
+			interconnect-names = "dma-mem", "write";
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		hsp_top2: hsp@1600000 {
 			compatible = "nvidia,tegra234-hsp";
 			reg = <0x0 0x1600000 0x0 0x90000>;