mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
07d664e800
Use SPDX license format in the header files. Change-Id: I84b9e439379c256762ca506348f293eeeeaf821b Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
81 lines
3.3 KiB
C
81 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Definitions for Jetson tegra234-p3767-0000 board.
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*/
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#include <dt-bindings/gpio/tegra234-gpio.h>
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#define JETSON_COMPATIBLE_P3768 "nvidia,p3768-0000+p3767-0000", \
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"nvidia,p3768-0000+p3767-0001", \
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"nvidia,p3768-0000+p3767-0003", \
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"nvidia,p3768-0000+p3767-0004", \
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"nvidia,p3768-0000+p3767-0005"
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#define JETSON_COMPATIBLE_P3509 "nvidia,p3509-0000+p3767-0000", \
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"nvidia,p3509-0000+p3767-0001", \
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"nvidia,p3509-0000+p3767-0003", \
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"nvidia,p3509-0000+p3767-0004", \
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"nvidia,p3509-0000+p3767-0005"
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#define JETSON_COMPATIBLE JETSON_COMPATIBLE_P3768, \
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JETSON_COMPATIBLE_P3509
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/* SoC function name for clock signal on 40-pin header pin 7 */
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#define HDR40_CLK "aud"
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/* SoC function name for I2S interface on 40-pin header pins 12, 35, 38 and 40 */
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#define HDR40_I2S "i2s2"
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/* SoC function name for SPI interface on 40-pin header pins 19, 21, 23, 24 and 26 */
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#define HDR40_SPI "spi1"
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/* SoC function name for UART interface on 40-pin header pins 8, 10, 11 and 36 */
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#define HDR40_UART "uarta"
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/* SoC pin name definitions for 40-pin header */
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#define HDR40_PIN7 "soc_gpio59_pac6"
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#define HDR40_PIN11 "uart1_rts_pr4"
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#define HDR40_PIN12 "soc_gpio41_ph7"
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#define HDR40_PIN13 "spi3_sck_py0"
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#define HDR40_PIN15 "soc_gpio39_pn1"
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#define HDR40_PIN16 "spi3_cs1_py4"
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#define HDR40_PIN18 "spi3_cs0_py3"
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#define HDR40_PIN19 "spi1_mosi_pz5"
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#define HDR40_PIN21 "spi1_miso_pz4"
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#define HDR40_PIN22 "spi3_miso_py1"
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#define HDR40_PIN23 "spi1_sck_pz3"
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#define HDR40_PIN24 "spi1_cs0_pz6"
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#define HDR40_PIN26 "spi1_cs1_pz7"
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#define HDR40_PIN29 "soc_gpio32_pq5"
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#define HDR40_PIN31 "soc_gpio33_pq6"
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#define HDR40_PIN32 "soc_gpio19_pg6"
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#define HDR40_PIN33 "soc_gpio21_ph0"
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#define HDR40_PIN35 "soc_gpio44_pi2"
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#define HDR40_PIN36 "uart1_cts_pr5"
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#define HDR40_PIN37 "spi3_mosi_py2"
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#define HDR40_PIN38 "soc_gpio43_pi1"
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#define HDR40_PIN40 "soc_gpio42_pi0"
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/* SoC GPIO definitions for 40-pin header */
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#define HDR40_PIN7_GPIO TEGRA_MAIN_GPIO(AC, 6)
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#define HDR40_PIN11_GPIO TEGRA_MAIN_GPIO(R, 4)
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#define HDR40_PIN12_GPIO TEGRA_MAIN_GPIO(H, 7)
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#define HDR40_PIN13_GPIO TEGRA_MAIN_GPIO(Y, 0)
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#define HDR40_PIN15_GPIO TEGRA_MAIN_GPIO(N, 1)
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#define HDR40_PIN16_GPIO TEGRA_AON_GPIO(Y, 4)
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#define HDR40_PIN18_GPIO TEGRA_MAIN_GPIO(Y, 3)
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#define HDR40_PIN19_GPIO TEGRA_MAIN_GPIO(Z, 5)
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#define HDR40_PIN21_GPIO TEGRA_MAIN_GPIO(Z, 4)
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#define HDR40_PIN22_GPIO TEGRA_MAIN_GPIO(Y, 1)
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#define HDR40_PIN23_GPIO TEGRA_MAIN_GPIO(Z, 3)
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#define HDR40_PIN24_GPIO TEGRA_MAIN_GPIO(Z, 6)
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#define HDR40_PIN26_GPIO TEGRA_MAIN_GPIO(Z, 7)
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#define HDR40_PIN29_GPIO TEGRA_AON_GPIO(Q, 5)
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#define HDR40_PIN31_GPIO TEGRA_AON_GPIO(Q, 6)
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#define HDR40_PIN32_GPIO TEGRA_AON_GPIO(G, 6)
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#define HDR40_PIN33_GPIO TEGRA_AON_GPIO(H, 0)
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#define HDR40_PIN35_GPIO TEGRA_MAIN_GPIO(I, 2)
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#define HDR40_PIN36_GPIO TEGRA_MAIN_GPIO(R, 5)
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#define HDR40_PIN37_GPIO TEGRA_AON_GPIO(Y, 2)
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#define HDR40_PIN38_GPIO TEGRA_MAIN_GPIO(I, 1)
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#define HDR40_PIN40_GPIO TEGRA_MAIN_GPIO(I, 0)
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