mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
acb70733aa
Update GPIO port macros to TEGRA234_MAIN_GPIO and TEGRA234_AON_GPIO to reference correct GPIO pin mappings. Bug 5430530 Change-Id: I100f2ddf3fff829805b8bbf88660637bf063d598 Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3422090 Reviewed-by: Hiteshkumar Patel <hiteshkumarg@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Prathamesh Shete <pshete@nvidia.com>
68 lines
2.8 KiB
C
68 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2021-2025, NVIDIA CORPORATION. All rights reserved.
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*
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* Definitions for Jetson tegra234-p3737-0000-p3701-0000 board.
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*/
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#include <dt-bindings/gpio/tegra234-gpio.h>
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#define JETSON_COMPATIBLE "nvidia,p3737-0000+p3701-0000", "nvidia,p3737-0000+p3701-0004", "nvidia,p3737-0000+p3701-0005", "nvidia,p3737-0000+p3701-0008"
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/* SoC function name for clock signal on 40-pin header pin 7 */
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#define HDR40_CLK "extperiph4"
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/* SoC function name for I2S interface on 40-pin header pins 12, 35, 38 and 40 */
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#define HDR40_I2S "i2s2"
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/* SoC function name for SPI interface on 40-pin header pins 19, 21, 23, 24 and 26 */
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#define HDR40_SPI "spi1"
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/* SoC function name for UART interface on 40-pin header pins 8, 10, 11 and 36 */
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#define HDR40_UART "uarta"
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/* SoC pin name definitions for 40-pin header */
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#define HDR40_PIN7 "soc_gpio33_pq6"
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#define HDR40_PIN11 "uart1_rts_pr4"
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#define HDR40_PIN12 "soc_gpio41_ph7"
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#define HDR40_PIN13 "soc_gpio37_pr0"
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#define HDR40_PIN15 "soc_gpio39_pn1"
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#define HDR40_PIN16 "can1_stb_pbb0"
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#define HDR40_PIN18 "soc_gpio21_ph0"
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#define HDR40_PIN19 "spi1_mosi_pz5"
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#define HDR40_PIN21 "spi1_miso_pz4"
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#define HDR40_PIN22 "soc_gpio23_pp4"
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#define HDR40_PIN23 "spi1_sck_pz3"
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#define HDR40_PIN24 "spi1_cs0_pz6"
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#define HDR40_PIN26 "spi1_cs1_pz7"
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#define HDR40_PIN29 "can0_din_paa1"
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#define HDR40_PIN31 "can0_dout_paa0"
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#define HDR40_PIN32 "can1_en_pbb1"
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#define HDR40_PIN33 "can1_dout_paa2"
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#define HDR40_PIN35 "soc_gpio44_pi2"
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#define HDR40_PIN36 "uart1_cts_pr5"
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#define HDR40_PIN37 "can1_din_paa3"
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#define HDR40_PIN38 "soc_gpio43_pi1"
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#define HDR40_PIN40 "soc_gpio42_pi0"
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/* SoC GPIO definitions for 40-pin header */
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#define HDR40_PIN7_GPIO TEGRA234_MAIN_GPIO(Q, 6)
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#define HDR40_PIN11_GPIO TEGRA234_MAIN_GPIO(R, 4)
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#define HDR40_PIN12_GPIO TEGRA234_MAIN_GPIO(H, 7)
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#define HDR40_PIN13_GPIO TEGRA234_MAIN_GPIO(R, 0)
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#define HDR40_PIN15_GPIO TEGRA234_MAIN_GPIO(N, 1)
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#define HDR40_PIN16_GPIO TEGRA234_AON_GPIO(BB, 0)
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#define HDR40_PIN18_GPIO TEGRA234_MAIN_GPIO(H, 0)
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#define HDR40_PIN19_GPIO TEGRA234_MAIN_GPIO(Z, 5)
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#define HDR40_PIN21_GPIO TEGRA234_MAIN_GPIO(Z, 4)
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#define HDR40_PIN22_GPIO TEGRA234_MAIN_GPIO(P, 4)
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#define HDR40_PIN23_GPIO TEGRA234_MAIN_GPIO(Z, 3)
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#define HDR40_PIN24_GPIO TEGRA234_MAIN_GPIO(Z, 6)
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#define HDR40_PIN26_GPIO TEGRA234_MAIN_GPIO(Z, 7)
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#define HDR40_PIN29_GPIO TEGRA234_AON_GPIO(AA, 1)
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#define HDR40_PIN31_GPIO TEGRA234_AON_GPIO(AA, 0)
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#define HDR40_PIN32_GPIO TEGRA234_AON_GPIO(BB, 1)
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#define HDR40_PIN33_GPIO TEGRA234_AON_GPIO(AA, 2)
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#define HDR40_PIN35_GPIO TEGRA234_MAIN_GPIO(I, 2)
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#define HDR40_PIN36_GPIO TEGRA234_MAIN_GPIO(R, 5)
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#define HDR40_PIN37_GPIO TEGRA234_AON_GPIO(AA, 3)
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#define HDR40_PIN38_GPIO TEGRA234_MAIN_GPIO(I, 1)
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#define HDR40_PIN40_GPIO TEGRA234_MAIN_GPIO(I, 0)
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