mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
18c086b748
Do the multiple minor alignment with mainline DTS/DTSI file
as follows:
- Rearranged the clock speed of serial port based on mainline.
- Corrected the pci3v3 regualotr GPIO on P3701-0000.
- Corrected usb phy-names on Pp3768-0000.
Bug 4037899
Change-Id: Ie39ede2eaed8f7eb0a2cbee6cdde47205a358c19
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2945863
(cherry picked from commit 9912826b40)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2955807
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
331 lines
6.2 KiB
Devicetree
331 lines
6.2 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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/dts-v1/;
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/plugin/;
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#include "tegra234-overlay.dtsi"
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#include "tegra234-soc-thermal.dtsi"
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#include "tegra234-soc-thermal-slowdown-cluster.dtsi"
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#include "tegra234-soc-thermal-shutdown.dtsi"
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#include "tegra234-p3767-0000.dtsi"
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/ {
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overlay-name = "Tegra234 P3768-0000+P3767-0000 Overlay";
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fragment-t234-p3768-p3767@0 {
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target-path = "/";
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__overlay__ {
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bus@0 {
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pinmux@2430000 {
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status = "okay";
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};
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/* UARTA, 40 pin header, Pin 8(TX), Pin 10(RX) */
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serial@3100000 {
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compatible = "nvidia,tegra194-hsuart";
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status = "okay";
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};
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/* UARTE, M2.E connector */
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serial@3140000 {
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compatible = "nvidia,tegra194-hsuart";
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status = "okay";
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};
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/* SPI1, 40pin header, Pin 19(MOSI), Pin 21(MISO), Pin 23(CLK), Pin 24(CS) */
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spi@3210000{
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status = "okay";
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spi@0 {
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compatible = "tegra-spidev";
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reg = <0x0>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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spi@1 {
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compatible = "tegra-spidev";
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reg = <0x1>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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};
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/* SPI3, 40pin header, Pin 37(MOSI), Pin 22(MISO), Pin 13(CLK), Pin 18(CS) */
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spi@3230000{
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status = "okay";
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spi@0 {
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compatible = "tegra-spidev";
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reg = <0x0>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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spi@1 {
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compatible = "tegra-spidev";
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reg = <0x1>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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};
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padctl@3520000 {
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ports {
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usb2-0 {
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port {
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typec_p0: endpoint {
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remote-endpoint = <&fusb_p0>;
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};
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};
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};
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};
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};
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i2c@c240000 {
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status = "okay";
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ina32211_1_40: ina3221@40 {
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compatible = "ti,ina3221";
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reg = <0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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#io-channel-cells = <1>;
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channel@0 {
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reg = <0x0>;
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label = "VDD_IN";
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shunt-resistor-micro-ohms = <5000>;
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};
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channel@1 {
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reg = <0x1>;
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label = "VDD_CPU_GPU_CV";
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shunt-resistor-micro-ohms = <5000>;
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};
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channel@2 {
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reg = <0x2>;
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label = "VDD_SOC";
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shunt-resistor-micro-ohms = <5000>;
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};
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};
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fusb301@25 {
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compatible = "onsemi,fusb301";
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reg = <0x25>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA234_MAIN_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
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connector@0 {
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port@0 {
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fusb_p0: endpoint {
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remote-endpoint = <&typec_p0>;
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};
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};
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};
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};
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};
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/* C1 - M.2 Key-E */
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pcie@14100000 {
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status = "okay";
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vddio-pex-ctl-supply = <&vdd_1v8_ao>;
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phys = <&p2u_hsio_3>;
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phy-names = "p2u-0";
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};
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/* C4 - M.2 Key-M */
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pcie@14160000 {
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status = "okay";
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vddio-pex-ctl-supply = <&vdd_1v8_ao>;
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phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
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<&p2u_hsio_7>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
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};
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/* C8 - Ethernet */
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pcie@140a0000 {
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status = "okay";
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num-lanes = <2>;
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phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
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phy-names = "p2u-0", "p2u-1";
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vddio-pex-ctl-supply = <&vdd_1v8_ao>;
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vpcie3v3-supply = <&vdd_3v3_pcie>;
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};
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/* C7 - M.2 Key-M */
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pcie@141e0000 {
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status = "okay";
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vddio-pex-ctl-supply = <&vdd_1v8_ao>;
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phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
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phy-names = "p2u-0", "p2u-1";
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};
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/* PWM1, 40pin header, pin 15 */
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pwm@3280000 {
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status = "okay";
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};
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/* PWM3, FAN */
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pwm@32a0000 {
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status = "okay";
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};
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/* PWM5, 40pin header, pin 33 */
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pwm@32c0000 {
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status = "okay";
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};
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/* PWM7, 40pin header, pin 32 */
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pwm@32e0000 {
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status = "okay";
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};
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serial@31d0000 {
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current-speed = <115200>;
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};
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tachometer@39c0000 {
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status = "okay";
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upper-threshold = <0xfffff>;
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lower-threshold = <0x0>;
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};
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hsp@3d00000 {
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status = "okay";
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};
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aon@c000000 {
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status = "okay";
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};
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mttcan@c310000 {
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status = "okay";
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};
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host1x@13e00000 {
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tegra_soc_hwpm {
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status = "okay";
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};
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nvdla0@15880000 {
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status = "okay";
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};
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nvdla1@158c0000 {
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status = "okay";
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};
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pva0@16000000 {
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status = "okay";
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pva0_niso1_ctx0 {
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status = "okay";
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};
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pva0_niso1_ctx1 {
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status = "okay";
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};
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pva0_niso1_ctx2 {
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status = "okay";
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};
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pva0_niso1_ctx3 {
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status = "okay";
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};
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pva0_niso1_ctx4 {
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status = "okay";
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};
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pva0_niso1_ctx5 {
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status = "okay";
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};
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pva0_niso1_ctx6 {
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status = "okay";
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};
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pva0_niso1_ctx7 {
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status = "okay";
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};
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};
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};
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};
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nvpmodel {
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status = "okay";
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};
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soctherm-oc-event {
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status = "okay";
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};
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thermal-zones {
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cpu-thermal {
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status = "okay";
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};
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gpu-thermal {
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status = "okay";
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};
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cv0-thermal {
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status = "okay";
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};
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cv1-thermal {
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status = "okay";
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};
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cv2-thermal {
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status = "okay";
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};
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soc0-thermal {
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status = "okay";
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};
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soc1-thermal {
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status = "okay";
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};
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soc2-thermal {
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status = "okay";
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};
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};
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};
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};
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};
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/*
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* Include this file last in the device tree. It manages run-time
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* pruning of peripherals that are not available across the various
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* SKUs of p3767. For example PVA can be enabled in the device tree
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* and it will automatically be disabled for SKUs without PVA support.
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*/
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#include "tegra234-p3767-sku-handling.dtsi"
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