mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
4d2010af58
The 'phy-mode' and 'power-domains' properties for the MGBE ethernet controller is present in the upstream SoC and platform files and so need to duplicate these properties in the SoC and platform overlay files. Bug 3820445 Bug 4293378 Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Change-Id: Ibf99701be0796a1b84db439c262a3f718587ab7b Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3082847 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Brad Griffis <bgriffis@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
148 lines
3.3 KiB
Devicetree
148 lines
3.3 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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/ {
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bus@0 {
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spi@3210000{ /* SPI1 in 40 pin conn */
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status = "okay";
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spi@0 { /* chip select 0 */
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compatible = "tegra-spidev";
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reg = <0x0>;
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spi-max-frequency = <50000000>;
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};
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spi@1 { /* chips select 1 */
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compatible = "tegra-spidev";
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reg = <0x1>;
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spi-max-frequency = <50000000>;
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};
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};
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spi@3230000{ /* SPI3 in 40 pin conn */
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status = "okay";
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spi@0 { /* chip select 0 */
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compatible = "tegra-spidev";
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reg = <0x0>;
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spi-max-frequency = <50000000>;
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};
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spi@1 { /* chips select 1 */
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compatible = "tegra-spidev";
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reg = <0x1>;
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spi-max-frequency = <50000000>;
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};
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};
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mmc@3400000 {
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vmmc-supply = <&vdd_3v3_sd>;
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};
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padctl@3520000 {
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ports {
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usb2-0 {
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mode = "otg";
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usb-role-switch;
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};
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};
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};
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aconnect@2900000 {
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ahub@2900800 {
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i2s@2901100 {
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ports {
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port@1 {
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hdr40_snd_i2s_dap_ep: endpoint {
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};
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};
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};
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};
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};
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};
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ethernet@6800000 {
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nvidia,mac-addr-idx = <0>;
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nvidia,max-platform-mtu = <16383>;
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/* 1=enable, 0=disable */
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nvidia,pause_frames = <1>;
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phy-handle = <&mgbe0_aqr113c_phy>;
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/* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */
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nvidia,phy-iface-mode = <0>;
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nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(Y, 1) 0>;
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nvidia,mdio_addr = <0>;
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mdio {
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compatible = "nvidia,eqos-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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mgbe0_aqr113c_phy: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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nvidia,phy-rst-pdelay-msec = <150>; /* msec */
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nvidia,phy-rst-duration-usec = <221000>; /* usec */
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA234_MAIN_GPIO(Y, 3) IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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};
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hdr40_vdd_3v3: regulator@3 {
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compatible = "regulator-fixed";
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reg = <3>;
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regulator-name = "vdd-3v3-sys";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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tegra_sound_graph: tegra_sound: sound {
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compatible = "nvidia,tegra186-audio-graph-card",
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"nvidia,tegra186-ape";
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clocks = <&bpmp TEGRA234_CLK_PLLA>,
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<&bpmp TEGRA234_CLK_PLLA_OUT0>,
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<&bpmp TEGRA234_CLK_AUD_MCLK>;
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clock-names = "pll_a", "plla_out0", "extern1";
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assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
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assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
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nvidia-audio-card,name = "NVIDIA Jetson AGX Orin APE";
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nvidia-audio-card,mclk-fs = <256>;
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hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { };
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};
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eeprom-manager {
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data-size = <0x100>;
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bus@0 {
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i2c-bus = <&gen1_i2c>;
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eeprom@1 {
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slave-address = <0x56>;
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label = "cvb";
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};
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};
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bus@1 {
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i2c-bus = <&cam_i2c>;
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eeprom@0 {
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slave-address = <0x54>;
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label = "sensor0";
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};
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eeprom@1 {
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slave-address = <0x57>;
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label = "sensor1";
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};
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eeprom@2 {
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slave-address = <0x52>;
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label = "sensor2";
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};
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};
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};
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vdd_3v3_sd: regulator-vdd-3v3-sd {
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compatible = "regulator-fixed";
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regulator-name = "VDD_3V3_SD";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio TEGRA234_MAIN_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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