t23x-public-dts/overlay/tegra234-p3767-sku-handling.dtsi

// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.

/ {
	p3767-sku-handling-fragment@0 {
		target-path = "/bus@0/host1x@13e00000";
		board_config {
			fuse-info = "fuse-disable-nvenc";
		};
		__overlay__ {
			nvenc@154c0000 {
				status = "disabled";
			};
		};
	};

	p3767-sku-handling-fragment@1 {
		target-path = "/bus@0/host1x@13e00000";
		board_config {
			fuse-info = "fuse-disable-pva";
		};
		__overlay__ {
			pva0@16000000 {
				status = "disabled";
			};
		};
	};

	p3767-sku-handling-fragment@2 {
		target-path = "/bus@0/host1x@13e00000";
		board_config {
			fuse-info = "fuse-disable-dla0";
		};
		__overlay__ {
			nvdla0@15880000 {
				status = "disabled";
			};
		};
	};

	p3767-sku-handling-fragment@3 {
		target-path = "/bus@0/host1x@13e00000";
		board_config {
			fuse-info = "fuse-disable-dla1";
		};
		__overlay__ {
			nvdla1@158c0000 {
				status = "disabled";
			};
		};
	};

	p3767-sku-handling-fragment@4 {
		target-path = "/bus@0";
		board_config {
			ids = "3767-0000-*","3767-0001-*","3767-0003-*","3767-0004-*";
		};
		__overlay__ {
			mmc@3400000 {
				status = "disabled";
			};
		};
	};

	/* For Orin Nano SKUs, reduce PCIe speed to Gen3 */
	p3767-sku-handling-fragment@5 {
		target-path = "/bus@0";
		board_config {
			ids = "3767-0003-*", "3767-0004-*", "3767-0005-*";
		};
		__overlay__ {
			/* C1 */
			pcie@14100000 {
				max-link-speed = <0x3>;
			};

			/* C4 */
			pcie@14160000 {
				max-link-speed = <0x3>;
			};

			/* C4 End Point */
			pcie_ep@14160000 {
				max-link-speed = <0x3>;
			};

			/* C7 */
			pcie@141e0000 {
				max-link-speed = <0x3>;
			};

			/* C8 */
			pcie@140a0000 {
				max-link-speed = <0x3>;
			};

			/* C9 */
			pcie@140c0000 {
				max-link-speed = <0x3>;
			};
		};
	};

	/*
	 * If ODMDATA contains gbe-uphy-config-9, then:
	 * 1. C7x1
	 * 2. C9x1
	 */
	p3767-sku-handling-fragment@6 {
		target-path = "/bus@0";
		board_config {
			odm-data = "gbe-uphy-config-9";
		};
		__overlay__ {
			/* C7 */
			pcie@141e0000 {
				phys = <&p2u_gbe_0>;
				phy-names = "p2u-0";
				num-lanes = <1>;
			};

			/* C9 */
			pcie@140c0000 {
				status = "okay";
				vddio-pex-ctl-supply = <&vdd_1v8_ao>;
				phys = <&p2u_gbe_1>;
				phy-names = "p2u-0";
				num-lanes = <1>;
			};
		};
	};
};