mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
deb67bdfad
The clock speed of the SBSA UART is configured in
common/base DTS file, hence remove the override of
this property from platform common override file.
Bug 4037899
Bug 4707773
Change-Id: Ib871ec7fe7561cfc42336d87125883a1fe224468
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3037843
(cherry picked from commit a7d01fe7f4)
Signed-off-by: Vedant Deshpande <vedantd@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3172851
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
Tested-by: Brad Griffis <bgriffis@nvidia.com>
472 lines
7.7 KiB
Devicetree
472 lines
7.7 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include "nv-soc/tegra234-overlay.dtsi"
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#include "nv-soc/tegra234-soc-thermal.dtsi"
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#include "nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi"
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#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
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#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
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#include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
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#include "tegra234-p3768-0000.dtsi"
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#include "tegra234-p3767-0000.dtsi"
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#include "nv-soc/tegra234-soc-camera.dtsi"
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#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
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#include <dt-bindings/gpio/tegra234-gpio.h>
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/ {
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aliases {
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serial1 = &uarta;
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serial2 = &uarte;
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};
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bpmp {
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i2c {
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vrs@3c {
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compatible = "nvidia,vrs-pseq";
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reg = <0x3c>;
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interrupt-parent = <&pmc>;
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/* VRS Wake ID is 24 */
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interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "okay";
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};
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};
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};
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bus@0 {
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actmon@d230000 {
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status = "okay";
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};
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pinmux@2430000 {
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status = "okay";
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};
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aconnect@2900000 {
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ahub@2900800 {
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i2s@2901200 {
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status = "okay";
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};
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i2s@2901400 {
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status = "okay";
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};
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dmic@2904000 {
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status = "okay";
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};
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dmic@2904100 {
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status = "okay";
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};
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dmic@2904300 {
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status = "okay";
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};
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dspk@2905000 {
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status = "okay";
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};
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dspk@2905100 {
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status = "okay";
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};
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afc@2907000 {
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status = "okay";
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};
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afc@2907100 {
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status = "okay";
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};
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afc@2907200 {
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status = "okay";
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};
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afc@2907300 {
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status = "okay";
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};
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afc@2907400 {
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status = "okay";
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};
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afc@2907500 {
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status = "okay";
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};
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arad@290e400 {
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status = "okay";
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};
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};
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};
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serial@3100000 {
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compatible = "nvidia,tegra194-hsuart";
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reset-names = "serial";
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status = "okay";
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};
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serial@3140000 {
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compatible = "nvidia,tegra194-hsuart";
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reset-names = "serial";
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status = "okay";
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};
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i2c@3180000 {
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status = "okay";
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};
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i2c@31b0000 {
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status = "okay";
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};
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hdr40_i2c1: i2c@c250000 {
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status = "okay";
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};
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/* SPI1, 40pin header, Pin 19(MOSI), Pin 21(MISO), Pin 23(CLK), Pin 24(CS) */
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spi@3210000{
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status = "okay";
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spi@0 {
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compatible = "tegra-spidev";
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reg = <0x0>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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spi@1 {
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compatible = "tegra-spidev";
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reg = <0x1>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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};
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/* SPI3, 40pin header, Pin 37(MOSI), Pin 22(MISO), Pin 13(CLK), Pin 18(CS) */
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spi@3230000{
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status = "okay";
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spi@0 {
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compatible = "tegra-spidev";
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reg = <0x0>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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spi@1 {
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compatible = "tegra-spidev";
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reg = <0x1>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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};
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padctl@3520000 {
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ports {
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usb2-0 {
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port {
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typec_p0: endpoint {
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remote-endpoint = <&fusb_p0>;
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};
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};
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};
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};
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};
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i2c@c240000 {
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status = "okay";
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ina32211_1_40: ina3221@40 {
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compatible = "ti,ina3221";
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reg = <0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0x0>;
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label = "VDD_IN";
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shunt-resistor-micro-ohms = <5000>;
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};
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channel@1 {
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reg = <0x1>;
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label = "VDD_CPU_GPU_CV";
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shunt-resistor-micro-ohms = <5000>;
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};
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channel@2 {
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reg = <0x2>;
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label = "VDD_SOC";
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shunt-resistor-micro-ohms = <5000>;
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};
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};
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fusb301@25 {
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compatible = "onsemi,fusb301";
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reg = <0x25>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA234_MAIN_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
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connector@0 {
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port@0 {
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fusb_p0: endpoint {
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remote-endpoint = <&typec_p0>;
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};
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};
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};
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};
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};
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/* C1 - M.2 Key-E */
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pcie@14100000 {
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status = "okay";
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vddio-pex-ctl-supply = <&vdd_1v8_ao>;
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phys = <&p2u_hsio_3>;
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phy-names = "p2u-0";
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};
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/* C4 - M.2 Key-M */
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pcie@14160000 {
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status = "okay";
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vddio-pex-ctl-supply = <&vdd_1v8_ao>;
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phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
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<&p2u_hsio_7>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
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};
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pcie-ep@14160000 {/* C4 - End Point */
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phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
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<&p2u_hsio_7>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
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reset-gpios = <&gpio
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TEGRA234_MAIN_GPIO(L, 1)
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GPIO_ACTIVE_LOW>;
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nvidia,refclk-select-gpios = <&gpio_aon
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TEGRA234_AON_GPIO(AA, 4)
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GPIO_ACTIVE_HIGH>;
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};
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/* C8 - Ethernet */
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pcie@140a0000 {
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status = "okay";
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num-lanes = <2>;
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phys = <&p2u_gbe_2>, <&p2u_gbe_3>;
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phy-names = "p2u-0", "p2u-1";
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vddio-pex-ctl-supply = <&vdd_1v8_ao>;
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vpcie3v3-supply = <&vdd_3v3_pcie>;
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};
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/* C7 - M.2 Key-M */
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pcie@141e0000 {
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status = "okay";
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vddio-pex-ctl-supply = <&vdd_1v8_ao>;
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phys = <&p2u_gbe_0>, <&p2u_gbe_1>;
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phy-names = "p2u-0", "p2u-1";
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};
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/* PWM1, 40pin header, pin 15 */
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pwm@3280000 {
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status = "okay";
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};
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/* PWM3, FAN */
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pwm@32a0000 {
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status = "okay";
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};
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/* PWM5, 40pin header, pin 33 */
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pwm@32c0000 {
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status = "okay";
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};
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/* PWM7, 40pin header, pin 32 */
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pwm@32e0000 {
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status = "okay";
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};
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tachometer@39c0000 {
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status = "okay";
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upper-threshold = <0xfffff>;
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lower-threshold = <0x0>;
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};
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hsp@3d00000 {
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status = "okay";
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};
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aon@c000000 {
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status = "okay";
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};
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hardware-timestamp@c1e0000 {
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status = "okay";
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nvidia,num-slices = <3>;
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};
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mttcan@c310000 {
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status = "okay";
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};
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hwpm@f100000 {
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status = "okay";
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};
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mc-hwpm@2c10000 {
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status = "okay";
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};
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host1x@13e00000 {
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nvdec@15480000 {
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status = "okay";
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};
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nvenc@154c0000 {
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status = "okay";
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};
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nvdla0@15880000 {
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status = "okay";
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};
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nvdla1@158c0000 {
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status = "okay";
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};
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ofa@15a50000 {
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status = "okay";
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};
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pva0@16000000 {
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status = "okay";
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pva0_niso1_ctx0 {
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status = "okay";
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};
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pva0_niso1_ctx1 {
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status = "okay";
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};
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pva0_niso1_ctx2 {
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status = "okay";
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};
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pva0_niso1_ctx3 {
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status = "okay";
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};
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pva0_niso1_ctx4 {
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status = "okay";
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};
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pva0_niso1_ctx5 {
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status = "okay";
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};
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pva0_niso1_ctx6 {
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status = "okay";
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};
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pva0_niso1_ctx7 {
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status = "okay";
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};
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};
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nvjpg@15380000 {
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status = "okay";
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};
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nvjpg@15540000 {
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status = "okay";
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};
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};
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};
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cpus {
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idle-states {
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c7 {
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status = "okay";
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};
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};
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};
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nvpmodel {
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status = "okay";
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};
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soctherm-oc-event {
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status = "okay";
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};
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thermal-zones {
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cpu-thermal {
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status = "okay";
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};
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gpu-thermal {
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status = "okay";
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};
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cv0-thermal {
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status = "okay";
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};
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cv1-thermal {
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status = "okay";
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};
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cv2-thermal {
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status = "okay";
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};
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soc0-thermal {
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status = "okay";
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};
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soc1-thermal {
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status = "okay";
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};
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soc2-thermal {
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status = "okay";
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};
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};
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dce@d800000 {
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status = "okay";
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};
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display@13800000 {
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/* os_gpio_hotplug_a is used for hotplug */
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os_gpio_hotplug_a = <&gpio TEGRA234_MAIN_GPIO(M, 0) GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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tegra-hsp@b950000 {
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status = "okay";
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};
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};
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