mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
6728ad5ff5
The node of "hardware-timestamp" is added in the base file but
there is no status property. Add status property and make as
disabled. The plafrom who needs these node will enable in their
respective DTS file.
Bug 4037899
Change-Id: I960eb024978aa4d424568b785433d2b295fb4f70
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2945730
(cherry picked from commit 133a575efc)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2955806
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
805 lines
20 KiB
Devicetree
805 lines
20 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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// This file contains the additional parameters which are missing from DT nodes of T234
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// available in base/tegra234.dtsi
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#include <dt-bindings/clock/tegra234-clock.h>
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#include <dt-bindings/reset/tegra234-reset.h>
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#include <dt-bindings/memory/tegra234-mc.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt/tegra234-irq.h>
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#include <dt-bindings/gpio/tegra234-gpio.h>
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#include <dt-bindings/p2u/tegra234-p2u.h>
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#include <dt-bindings/power/tegra234-powergate.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#define TEGRA234_POWER_DOMAIN_PVA 30U
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#define TEGRA234_POWER_DOMAIN_GPU 35U
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#define TEGRA234_POWER_DOMAIN_DLAA 32U
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#define TEGRA234_POWER_DOMAIN_DLAB 33U
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/ {
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overlay-name = "Add nvidia,t234 Overlay Support";
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compatible = "nvidia,tegra234";
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fragment-t234-base@0 {
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target-path = "/";
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__overlay__ {
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aliases {
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serial0 = "/bus@0/serial@3100000";
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serial1 = "/bus@0/serial@3110000";
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serial2 = "/bus@0/serial@3140000";
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i2c0 = "/bus@0/i2c@3160000";
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i2c1 = "/bus@0/i2c@c240000";
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i2c2 = "/bus@0/i2c@3180000";
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i2c3 = "/bus@0/i2c@3190000";
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i2c4 = "/bpmp/i2c";
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i2c5 = "/bus@0/i2c@31b0000";
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i2c6 = "/bus@0/i2c@31c0000";
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i2c7 = "/bus@0/i2c@c250000";
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i2c8 = "/bus@0/i2c@31e0000";
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qspi0 = "/bus@0/spi@3270000";
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};
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bus@0 {
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pcie@140a0000 {
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iommus = <&smmu_niso1 TEGRA234_SID_PCIE8>;
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};
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pcie@140c0000 {
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iommus = <&smmu_niso0 TEGRA234_SID_PCIE9>;
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};
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pcie@140e0000 {
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iommus = <&smmu_niso1 TEGRA234_SID_PCIE10>;
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};
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pcie@14100000 {
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iommus = <&smmu_niso1 TEGRA234_SID_PCIE1>;
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};
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pcie@14120000 {
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iommus = <&smmu_niso1 TEGRA234_SID_PCIE2>;
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};
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pcie@14140000 {
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iommus = <&smmu_niso1 TEGRA234_SID_PCIE3>;
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};
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pcie@14160000 {
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iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>;
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};
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pcie@14180000 {
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iommus = <&smmu_niso0 TEGRA234_SID_PCIE0>;
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};
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pcie@141a0000 {
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iommus = <&smmu_niso0 TEGRA234_SID_PCIE5>;
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};
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pcie@141c0000 {
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iommus = <&smmu_niso0 TEGRA234_SID_PCIE6>;
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};
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pcie@141e0000 {
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iommus = <&smmu_niso1 TEGRA234_SID_PCIE7>;
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};
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pcie-ep@141a0000 {
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iommus = <&smmu_niso0 TEGRA234_SID_PCIE5>;
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};
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pcie-ep@141c0000{
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iommus = <&smmu_niso0 TEGRA234_SID_PCIE6>;
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};
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pcie-ep@141e0000{
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iommus = <&smmu_niso1 TEGRA234_SID_PCIE7>;
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};
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pcie-ep@140e0000{
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iommus = <&smmu_niso1 TEGRA234_SID_PCIE10>;
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};
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hda@3510000 {
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iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
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};
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aconnect@2900000 {
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ahub@2900800 {
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assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
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<&bpmp TEGRA234_CLK_PLLA_OUT0>,
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<&bpmp TEGRA234_CLK_AHUB>;
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assigned-clock-parents = <0>,
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<&bpmp TEGRA234_CLK_PLLA>,
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<&bpmp TEGRA234_CLK_PLLP_OUT0>;
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assigned-clock-rates = <294912000>,
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<49152000>,
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<81600000>;
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#sound-dai-cells = <1>;
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/*
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* Below modules are upstreamed and present in v5.15,
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* but not yet feature complete. Thus use OOT driver
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* versions for now.
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*/
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i2s@2901000 {
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#sound-dai-cells = <1>;
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nvidia,ahub-i2s-id = <0>;
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};
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i2s@2901100 {
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#sound-dai-cells = <1>;
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nvidia,ahub-i2s-id = <1>;
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};
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i2s@2901200 {
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#sound-dai-cells = <1>;
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nvidia,ahub-i2s-id = <2>;
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};
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i2s@2901300 {
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#sound-dai-cells = <1>;
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nvidia,ahub-i2s-id = <3>;
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};
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i2s@2901400 {
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#sound-dai-cells = <1>;
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nvidia,ahub-i2s-id = <4>;
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};
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i2s@2901500 {
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#sound-dai-cells = <1>;
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nvidia,ahub-i2s-id = <5>;
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};
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dmic@2904000 {
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#sound-dai-cells = <1>;
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};
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dmic@2904100 {
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#sound-dai-cells = <1>;
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};
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dmic@2904200 {
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#sound-dai-cells = <1>;
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};
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dmic@2904300 {
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#sound-dai-cells = <1>;
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};
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dspk@2905000 {
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#sound-dai-cells = <1>;
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};
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dspk@2905100 {
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#sound-dai-cells = <1>;
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};
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admaif@290f000 {
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#sound-dai-cells = <1>;
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};
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/*
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* Below modules are upstreamed. DT device nodes
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* are backported. But drivers are not in v5.15.
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* Thus use existing downstream drivers and add
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* '#sound-dai-cells' property needed for downstream
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* machine driver.
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*/
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sfc@2902000 {
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#sound-dai-cells = <1>;
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};
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sfc@2902200 {
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#sound-dai-cells = <1>;
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};
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sfc@2902400 {
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#sound-dai-cells = <1>;
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};
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sfc@2902600 {
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#sound-dai-cells = <1>;
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};
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amx@2903000 {
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#sound-dai-cells = <1>;
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};
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amx@2903100 {
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#sound-dai-cells = <1>;
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};
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amx@2903200 {
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#sound-dai-cells = <1>;
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};
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amx@2903300 {
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#sound-dai-cells = <1>;
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};
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adx@2903800 {
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#sound-dai-cells = <1>;
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};
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adx@2903900 {
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#sound-dai-cells = <1>;
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};
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adx@2903a00 {
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#sound-dai-cells = <1>;
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};
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adx@2903b00 {
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#sound-dai-cells = <1>;
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};
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mvc@290a000 {
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#sound-dai-cells = <1>;
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};
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mvc@290a200 {
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#sound-dai-cells = <1>;
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};
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amixer@290bb00 {
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#sound-dai-cells = <1>;
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};
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processing-engine@2908000 {
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#sound-dai-cells = <1>;
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};
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asrc@2910000 {
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#sound-dai-cells = <1>;
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};
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};
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/*
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* Placeholder for ADSP audio device.
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* Not required for L4T releases, will be
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* enabled as and when needed.
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*/
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tegra_adsp_audio: adsp_audio {
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#sound-dai-cells = <1>;
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status = "disabled";
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};
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};
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ethernet@2310000 {
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compatible = "nvidia,nveqos";
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reg = <0x0 0x02310000 0x0 0x10000>, /* EQOS Base Register */
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<0x0 0x023D0000 0x0 0x10000>, /* MACSEC Base Register */
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<0x0 0x02300000 0x0 0x10000>; /* HV Base Register */
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reg-names = "mac", "macsec-base", "hypervisor";
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interrupts = <0 194 0x4>, /* common */
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<0 186 0x4>, /* vm0 */
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<0 187 0x4>, /* vm1 */
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<0 188 0x4>, /* vm2 */
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<0 189 0x4>, /* vm3 */
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<0 190 0x4>, /* MACsec non-secure intr */
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<0 191 0x4>; /* MACsec secure intr */
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interrupt-names = "common", "vm0", "vm1", "vm2", "vm3",
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"macsec-ns-irq", "macsec-s-irq";
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resets = <&bpmp TEGRA234_RESET_EQOS>,
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<&bpmp TEGRA234_RESET_EQOS_MACSEC>; /* MACsec non-secure reset */
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reset-names = "mac", "macsec_ns_rst";
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clocks = <&bpmp TEGRA234_CLK_PLLREFE_VCOOUT>,
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<&bpmp TEGRA234_CLK_EQOS_AXI>,
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<&bpmp TEGRA234_CLK_EQOS_RX>,
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<&bpmp TEGRA234_CLK_EQOS_PTP_REF>,
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<&bpmp TEGRA234_CLK_EQOS_TX>,
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<&bpmp TEGRA234_CLK_AXI_CBB>,
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<&bpmp TEGRA234_CLK_EQOS_RX_M>,
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<&bpmp TEGRA234_CLK_EQOS_RX_INPUT>,
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<&bpmp TEGRA234_CLK_EQOS_MACSEC_TX>,
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<&bpmp TEGRA234_CLK_EQOS_TX_DIVIDER>,
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<&bpmp TEGRA234_CLK_EQOS_MACSEC_RX>;
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clock-names = "pllrefe_vcoout", "eqos_axi", "eqos_rx",
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"eqos_ptp_ref", "eqos_tx", "axi_cbb",
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"eqos_rx_m", "eqos_rx_input",
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"eqos_macsec_tx", "eqos_tx_divider",
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"eqos_macsec_rx";
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#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>,
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<&mc TEGRA234_MEMORY_CLIENT_EQOSW>;
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interconnect-names = "dma-mem", "write";
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#endif
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iommus = <&smmu_niso1 TEGRA234_SID_EQOS>;
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nvidia,num-dma-chans = <8>;
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nvidia,num-mtl-queues = <8>;
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nvidia,mtl-queues = <0 1 2 3 4 5 6 7>;
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nvidia,dma-chans = <0 1 2 3 4 5 6 7>;
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nvidia,tc-mapping = <0 1 2 3 4 5 6 7>;
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/* Residual Queue can be any valid queue except RxQ0 */
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nvidia,residual-queue = <1>;
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nvidia,rx-queue-prio = <0x2 0x1 0x30 0x48 0x0 0x0 0x0 0x0>;
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nvidia,tx-queue-prio = <0x0 0x7 0x2 0x3 0x0 0x0 0x0 0x0>;
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nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2>;
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nvidia,vm-irq-config = <&eqos_vm_irq_config>;
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status = "disabled";
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nvidia,dcs-enable = <0x1>;
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nvidia,macsec-enable = <0x1>;
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nvidia,pad_calibration = <0x1>;
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/* pad calibration 2's complement offset for pull-down value */
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nvidia,pad_auto_cal_pd_offset = <0x0>;
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/* pad calibration 2's complement offset for pull-up value */
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nvidia,pad_auto_cal_pu_offset = <0x0>;
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nvidia,rx_riwt = <512>;
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nvidia,rx_frames = <64>;
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nvidia,tx_usecs = <256>;
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nvidia,tx_frames = <5>;
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nvidia,promisc_mode = <1>;
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nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
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nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
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nvidia,ptp_ref_clock_speed = <208333334>;
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nvidia,instance_id = <4>; /* EQOS instance */
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nvidia,ptp-rx-queue = <3>;
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pinctrl-names = "mii_rx_disable", "mii_rx_enable";
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pinctrl-0 = <&eqos_mii_rx_input_state_disable>;
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pinctrl-1 = <&eqos_mii_rx_input_state_enable>;
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nvidia,dma_rx_ring_sz = <1024>;
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nvidia,dma_tx_ring_sz = <1024>;
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dma-coherent;
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};
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ethernet@6800000 {
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compatible = "nvidia,tegra234-mgbe";
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reg = <0x0 0x06810000 0x0 0x10000>, /* MGBE base */
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<0x0 0x068A0000 0x0 0x10000>, /* XPCS base */
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<0x0 0x068D0000 0x0 0x10000>, /* MACsec RM base */
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<0x0 0x06800000 0x0 0x10000>; /* HV base */
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reg-names = "mac", "xpcs", "macsec-base", "hypervisor";
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interrupts = <0 384 0x4>, /* common */
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<0 385 0x4>, /* vm0 */
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<0 386 0x4>, /* vm1 */
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<0 387 0x4>, /* vm2 */
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<0 388 0x4>, /* vm3 */
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<0 389 0x4>, /* vm4 */
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<0 390 0x4>, /* MACsec non-secure intr */
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<0 391 0x4>; /* MACsec secure intr */
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interrupt-names = "common", "vm0", "vm1", "vm2", "vm3", "vm4",
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"macsec-ns-irq", "macsec-s-irq";
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resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
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<&bpmp TEGRA234_RESET_MGBE0_PCS>,
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<&bpmp TEGRA234_RESET_MGBE0_MACSEC>; /* MACsec non-secure reset */
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reset-names = "mac", "pcs", "macsec_ns_rst";
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clocks = <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
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<&bpmp TEGRA234_CLK_MGBE0_TX>,
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<&bpmp TEGRA234_CLK_MGBE0_TX_PCS>,
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<&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
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<&bpmp TEGRA234_CLK_MGBE0_MAC>,
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<&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
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<&bpmp TEGRA234_CLK_MGBE0_APP>,
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<&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
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<&bpmp TEGRA234_CLK_MGBE0_MACSEC>,
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<&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>;
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clock-names = "rx-input-m", "rx-pcs-m", "rx-pcs-input",
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"rx-pcs", "tx", "tx-pcs", "mac-divider",
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"mac", "eee-pcs", "mgbe", "ptp-ref",
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"mgbe_macsec", "rx-input";
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD>,
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<&mc TEGRA234_MEMORY_CLIENT_MGBEAWR>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
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nvidia,vm-irq-config = <&mgbe_vm_irq_config>;
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nvidia,num-dma-chans = <10>;
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nvidia,dma-chans = <0 1 2 3 4 5 6 7 8 9>;
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nvidia,num-mtl-queues = <10>;
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nvidia,mtl-queues = <0 1 2 3 4 5 6 7 8 9>;
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nvidia,tc-mapping = <0 1 2 3 4 5 6 7 0 1>;
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/* Residual Queue can be any valid queue except RxQ0 */
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nvidia,residual-queue = <1>;
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nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2 2 2>;
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nvidia,tx-queue-prio = <0 1 2 3 4 5 6 7 0 0>;
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nvidia,rx-queue-prio = <0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80 0x0 0x0>;
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nvidia,dcs-enable = <0x1>;
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nvidia,macsec-enable = <0x1>;
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nvidia,rx_riwt = <512>;
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nvidia,rx_frames = <64>;
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nvidia,tx_usecs = <256>;
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nvidia,tx_frames = <16>;
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nvidia,promisc_mode = <1>;
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nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
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nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
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nvidia,ptp_ref_clock_speed = <312500000>;
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nvidia,instance_id = <0>; /* MGBE0 instance */
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nvidia,ptp-rx-queue = <3>;
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nvidia,dma_rx_ring_sz = <4096>;
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nvidia,dma_tx_ring_sz = <4096>;
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dma-coherent;
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};
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host1x@13e00000 {
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interrupt-parent = <&gic>;
|
|
|
|
ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>,
|
|
<0x0 0x24700000 0x0 0x24700000 0x0 0x00080000>;
|
|
};
|
|
|
|
spi@3270000 {
|
|
reset-names = "qspi";
|
|
dma-names = "rx", "tx";
|
|
dma-coherent;
|
|
iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>;
|
|
};
|
|
|
|
spi@3300000 {
|
|
reset-names = "qspi";
|
|
};
|
|
|
|
hardware-timestamp@3aa0000 {
|
|
status = "disabled";
|
|
};
|
|
|
|
hardware-timestamp@c1e0000 {
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@3160000 {
|
|
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
|
dma-coherent;
|
|
};
|
|
|
|
i2c@3180000 {
|
|
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
|
dma-coherent;
|
|
};
|
|
|
|
i2c@3190000 {
|
|
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
|
dma-coherent;
|
|
};
|
|
|
|
i2c@31b0000 {
|
|
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
|
dma-coherent;
|
|
};
|
|
|
|
i2c@31c0000 {
|
|
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
|
dma-coherent;
|
|
};
|
|
|
|
i2c@31e0000 {
|
|
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
|
dma-coherent;
|
|
};
|
|
|
|
i2c@c240000 {
|
|
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
|
dma-coherent;
|
|
};
|
|
|
|
i2c@c250000 {
|
|
nvidia,hw-instance-id = <0x7>;
|
|
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
|
dma-coherent;
|
|
};
|
|
|
|
pwm@3280000 {
|
|
compatible = "nvidia,tegra234-pwm",
|
|
"nvidia,tegra194-pwm";
|
|
};
|
|
|
|
phy@3e00000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L0_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID0>;
|
|
};
|
|
|
|
phy@3e10000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L1_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID1>;
|
|
};
|
|
|
|
phy@3e20000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L2_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID2>;
|
|
};
|
|
|
|
phy@3e30000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L3_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID3>;
|
|
};
|
|
|
|
phy@3e40000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L4_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID4>;
|
|
};
|
|
|
|
phy@3e50000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L5_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID5>;
|
|
};
|
|
|
|
phy@3e60000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L6_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID6>;
|
|
};
|
|
|
|
phy@3e70000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L7_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID7>;
|
|
};
|
|
|
|
phy@3e90000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L0_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID8>;
|
|
};
|
|
|
|
phy@3ea0000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L1_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID9>;
|
|
};
|
|
|
|
phy@3eb0000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L2_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID10>;
|
|
};
|
|
|
|
phy@3ec0000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L3_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID11>;
|
|
};
|
|
|
|
phy@3ed0000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L4_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID12>;
|
|
};
|
|
|
|
phy@3ee0000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L5_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID13>;
|
|
};
|
|
|
|
phy@3ef0000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L6_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID14>;
|
|
};
|
|
|
|
phy@3f00000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L7_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID15>;
|
|
};
|
|
|
|
phy@3f20000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L0_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID16>;
|
|
};
|
|
|
|
phy@3f30000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L1_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID17>;
|
|
};
|
|
|
|
phy@3f40000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L2_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID18>;
|
|
};
|
|
|
|
phy@3f50000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L3_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID19>;
|
|
};
|
|
|
|
phy@3f60000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L4_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID20>;
|
|
};
|
|
|
|
phy@3f70000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L5_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID21>;
|
|
};
|
|
|
|
phy@3f80000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L6_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID22>;
|
|
};
|
|
|
|
phy@3f90000 {
|
|
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L7_P2U IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "intr";
|
|
|
|
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID23>;
|
|
};
|
|
|
|
mmc@3460000 {
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
mmc-hs400-1_8v;
|
|
mmc-hs400-enhanced-strobe;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
};
|
|
|
|
serial@3100000 {
|
|
clock-names = "serial";
|
|
reset-names = "serial";
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
idle-states {
|
|
entry-method = "psci";
|
|
|
|
C7: c7 {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x40000007>;
|
|
min-residency-us = <30000>;
|
|
wakeup-latency-us = <5000>;
|
|
idle-state-name = "Core powergate";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
cpu@0 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@100 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@200 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@300 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@10000 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@10100 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@10200 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@10300 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@20000 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@20100 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@20200 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
|
|
cpu@20300 {
|
|
cpu-idle-states = <&C7>;
|
|
};
|
|
};
|
|
|
|
mgbe_vm_irq_config: mgbe-vm-irq-config {
|
|
nvidia,num-vm-irqs = <5>;
|
|
vm_irq1 {
|
|
nvidia,num-vm-channels = <2>;
|
|
nvidia,vm-channels = <0 1>;
|
|
nvidia,vm-num = <0>;
|
|
nvidia,vm-irq-id = <0>;
|
|
};
|
|
vm_irq2 {
|
|
nvidia,num-vm-channels = <2>;
|
|
nvidia,vm-channels = <2 3>;
|
|
nvidia,vm-num = <1>;
|
|
nvidia,vm-irq-id = <1>;
|
|
};
|
|
vm_irq3 {
|
|
nvidia,num-vm-channels = <2>;
|
|
nvidia,vm-channels = <4 5>;
|
|
nvidia,vm-num = <2>;
|
|
nvidia,vm-irq-id = <2>;
|
|
};
|
|
vm_irq4 {
|
|
nvidia,num-vm-channels = <2>;
|
|
nvidia,vm-channels = <6 7>;
|
|
nvidia,vm-num = <3>;
|
|
nvidia,vm-irq-id = <3>;
|
|
};
|
|
vm_irq5 {
|
|
nvidia,num-vm-channels = <2>;
|
|
nvidia,vm-channels = <8 9>;
|
|
nvidia,vm-num = <4>;
|
|
nvidia,vm-irq-id = <4>;
|
|
};
|
|
};
|
|
|
|
eqos_vm_irq_config: vm-irq-config {
|
|
nvidia,num-vm-irqs = <4>;
|
|
vm_irq1 {
|
|
nvidia,num-vm-channels = <2>;
|
|
nvidia,vm-channels = <0 1>;
|
|
nvidia,vm-num = <0>;
|
|
nvidia,vm-irq-id = <0>;
|
|
};
|
|
vm_irq2 {
|
|
nvidia,num-vm-channels = <2>;
|
|
nvidia,vm-channels = <2 3>;
|
|
nvidia,vm-num = <1>;
|
|
nvidia,vm-irq-id = <1>;
|
|
};
|
|
vm_irq3 {
|
|
nvidia,num-vm-channels = <2>;
|
|
nvidia,vm-channels = <4 5>;
|
|
nvidia,vm-num = <2>;
|
|
nvidia,vm-irq-id = <2>;
|
|
};
|
|
vm_irq4 {
|
|
nvidia,num-vm-channels = <2>;
|
|
nvidia,vm-channels = <6 7>;
|
|
nvidia,vm-num = <3>;
|
|
nvidia,vm-irq-id = <3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|