mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
ee6247a701
In this commit: 1. The large platform overlays are being directly built into a new base "nv" dtb. The names of these new dtbs directly tracks the name of the upstream dtb that it extends. For an upstream dtb named <base>.dtb the new corresponding new file is named <base>-nv.dtb. 2. The source files for <base>-nv.dtb are located in the nv-soc/ and nv-platform/ files. Those files originated in the overlay/ directory but are moved to reflect that they are no longer part of an overlay. This new layout seeks to simplify building and handling of dtb files while retaining close compatibility with the upstream dts sources. Bug 4290389 Change-Id: Ic812e8e16c5515bb3e17b99a23815a99f67c42a2 Signed-off-by: Brad Griffis <bgriffis@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2996468 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Gautham Srinivasan <gauthams@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
356 lines
10 KiB
Devicetree
356 lines
10 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/clock/tegra234-clock.h>
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#include <dt-bindings/gpio/tegra234-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/memory/tegra234-mc.h>
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#include <dt-bindings/power/tegra234-powergate.h>
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#include <dt-bindings/reset/tegra234-reset.h>
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#include "nv-soc/tegra234-soc-display-overlay.dtsi"
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#include "nv-platform/tegra234-dcb-p3737-0000-p3701-0000.dtsi"
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/ {
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overlay-name = "Tegra234 Jetson Overlay";
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compatible = "nvidia,tegra234";
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fragment@0 {
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target-path = "/bus@0/host1x@13e00000";
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges = <0x14800000 0x14800000 0x02000000>,
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<0x24700000 0x24700000 0x00080000>;
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nvjpg@15380000 {
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compatible = "nvidia,tegra234-nvjpg";
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reg = <0x15380000 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVJPG>;
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clock-names = "nvjpg";
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resets = <&bpmp TEGRA234_RESET_NVJPG>;
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reset-names = "nvjpg";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGA>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPGSRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVJPGSWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso1 TEGRA234_SID_NVJPG>;
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dma-coherent;
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nvidia,host1x-class = <0xc0>;
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};
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nvdec@15480000 {
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compatible = "nvidia,tegra234-nvdec";
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reg = <0x15480000 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVDEC>,
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<&bpmp TEGRA234_CLK_FUSE>,
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<&bpmp TEGRA234_CLK_TSEC_PKA>;
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clock-names = "nvdec", "fuse", "tsec_pka";
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resets = <&bpmp TEGRA234_RESET_NVDEC>;
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reset-names = "nvdec";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
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dma-coherent;
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nvidia,memory-controller = <&mc>;
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status = "okay";
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};
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nvenc@154c0000 {
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compatible = "nvidia,tegra234-nvenc";
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reg = <0x154c0000 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVENC>;
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clock-names = "nvenc";
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resets = <&bpmp TEGRA234_RESET_NVENC>;
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reset-names = "nvenc";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVENC>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVENCSRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVENCSWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_NVENC>;
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dma-coherent;
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};
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nvjpg@15540000 {
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compatible = "nvidia,tegra234-nvjpg";
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reg = <0x15540000 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_NVJPG1>;
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clock-names = "nvjpg";
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resets = <&bpmp TEGRA234_RESET_NVJPG1>;
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reset-names = "nvjpg";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVJPGB>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVJPG1SRD &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVJPG1SWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_NVJPG1>;
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dma-coherent;
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nvidia,host1x-class = <0x07>;
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};
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nvdla0: nvdla0@15880000 {
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compatible = "nvidia,tegra234-nvdla";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAA>;
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reg = <0x15880000 0x00040000>;
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interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&bpmp TEGRA234_RESET_DLA0>;
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clocks = <&bpmp TEGRA234_CLK_DLA0_CORE>,
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<&bpmp TEGRA234_CLK_DLA0_FALCON>;
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clock-names = "nvdla0", "nvdla0_flcn";
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA0RDA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA0FALRDB &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA0WRA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA0FALWRB &emc>;
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interconnect-names = "dma-mem", "read-1", "write", "write-1";
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iommus = <&smmu_niso1 TEGRA234_SID_NVDLA0>;
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dma-coherent;
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status = "okay";
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};
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nvdla1: nvdla1@158c0000 {
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compatible = "nvidia,tegra234-nvdla";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAB>;
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reg = <0x158c0000 0x00040000>;
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interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&bpmp TEGRA234_RESET_DLA1>;
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clocks = <&bpmp TEGRA234_CLK_DLA1_CORE>,
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<&bpmp TEGRA234_CLK_DLA1_FALCON>;
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clock-names = "nvdla1", "nvdla1_flcn";
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_DLA1RDA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA1FALRDB &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA1WRA &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_DLA1FALWRB &emc>;
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interconnect-names = "dma-mem", "read-1", "write", "write-1";
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iommus = <&smmu_niso0 TEGRA234_SID_NVDLA1>;
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dma-coherent;
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status = "okay";
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};
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ofa@15a50000 {
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compatible = "nvidia,tegra234-ofa";
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reg = <0x15a50000 0x00040000>;
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clocks = <&bpmp TEGRA234_CLK_OFA>;
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clock-names = "ofa";
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resets = <&bpmp TEGRA234_RESET_OFA>;
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reset-names = "ofa";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_OFA>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_OFAR &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_OFAW &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu_niso0 TEGRA234_SID_OFA>;
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dma-coherent;
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};
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pva0: pva0@16000000 {
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compatible = "nvidia,tegra234-pva";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PVA>;
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reg = <0x16000000 0x800000>,
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<0x24700000 0x080000>;
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interrupts = <0 234 0x04>,
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<0 432 0x04>,
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<0 433 0x04>,
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<0 434 0x04>,
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<0 435 0x04>,
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<0 436 0x04>,
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<0 437 0x04>,
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<0 438 0x04>,
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<0 439 0x04>;
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resets = <&bpmp TEGRA234_RESET_PVA0_ALL>;
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clocks = <&bpmp TEGRA234_CLK_PVA0_CPU_AXI>,
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<&bpmp TEGRA234_CLK_NAFLL_PVA0_VPS>,
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<&bpmp TEGRA234_CLK_PVA0_VPS>;
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clock-names = "axi", "vps0", "vps1";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0>;
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dma-coherent;
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status = "okay";
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pva0_ctx0n1: pva0_niso1_ctx0 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM0>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx1n1: pva0_niso1_ctx1 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM1>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx2n1: pva0_niso1_ctx2 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM2>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx3n1: pva0_niso1_ctx3 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM3>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx4n1: pva0_niso1_ctx4 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM4>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx5n1: pva0_niso1_ctx5 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM5>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx6n1: pva0_niso1_ctx6 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM6>;
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dma-coherent;
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status = "okay";
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};
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pva0_ctx7n1: pva0_niso1_ctx7 {
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compatible = "nvidia,pva-tegra186-iommu-context";
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iommus = <&smmu_niso1 TEGRA234_SID_PVA0_VM7>;
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dma-coherent;
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status = "okay";
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};
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};
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};
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};
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fragment@1 {
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target-path = "/bus@0";
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <1>;
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gpu@17000000 {
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compatible = "nvidia,ga10b";
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reg = <0x17000000 0x01000000>,
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<0x18000000 0x01000000>,
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<0x03b41000 0x00001000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "stall0", "stall1", "stall2", "nonstall";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_GPU>;
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interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVL1R &emc>,
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<&mc TEGRA234_MEMORY_CLIENT_NVL1W &emc>;
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interconnect-names = "dma-mem", "write";
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clocks = <&bpmp TEGRA234_CLK_GPUSYS>,
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<&bpmp TEGRA234_CLK_GPC0CLK>,
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<&bpmp TEGRA234_CLK_GPC1CLK>;
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clock-names = "sysclk", "gpc0clk", "gpc1clk";
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resets = <&bpmp TEGRA234_RESET_GPU>;
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dma-coherent;
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nvidia,bpmp = <&bpmp>;
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status = "okay";
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};
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tachometer@39c0000 {
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compatible = "nvidia,pwm-tegra234-tachometer";
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reg = <0x039c0000 0x10>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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#pwm-cells = <2>;
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clocks = <&bpmp TEGRA234_CLK_TACH0>;
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clock-names = "tach";
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resets = <&bpmp TEGRA234_RESET_TACH0>;
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reset-names = "tach";
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pulse-per-rev = <2>;
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capture-window-length = <2>;
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upper-threshold = <0xfffff>;
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lower-threshold = <0x0>;
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};
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};
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};
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fragment@2 {
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target-path = "/";
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__overlay__ {
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nvpmodel {
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compatible = "nvidia,nvpmodel";
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nvidia,bpmp = <&bpmp>;
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clocks = <&bpmp TEGRA234_CLK_EMC>;
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clock-names = "emc";
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status = "okay";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma { /* Needed for nvgpu comptags */
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x10000000>; /* 256MB */
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alignment = <0x0 0x10000>;
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linux,cma-default;
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status = "okay";
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};
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};
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dce@d800000 {
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status = "okay";
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};
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display@13800000 {
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status = "okay";
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};
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};
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};
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fragment@3 {
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target-path = "/bus@0";
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board_config {
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ids = "3737-0000-TS1","3737-0000-TS2","3737-0000-TS3","3737-0000-EB1","3737-0000-EB2","3737-0000-EB3","3737-0000-000","3737-0000-100","3737-0000-200";
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};
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__overlay__ {
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i2c@c240000 {
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ucsi_ccg@8 {
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interrupt-parent = <&gpio_aon>;
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interrupts = <TEGRA234_AON_GPIO(BB, 2) IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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};
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fragment@5 {
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target-path = "/";
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__overlay__ {
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aliases {
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nvdla0 = "/bus@0/host1x@13e00000/nvdla0@15880000";
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nvdla1 = "/bus@0/host1x@13e00000/nvdla1@158c0000";
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};
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};
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};
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};
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