mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
782ead6230
As part of the process to transitioning to a full featured
base dtb, we need the ability to include various files without
completely rewriting them. This will be an incremental step.
Eventually these preprocessor commands will be removed and
the indentation fixed.
This change is not intended to change any behavior. It is merely
adding the infrastructure for future patches. It will be possible
for a base dts file to define REMOVE_FRAGMENT_SYNTAX and directly
include these files.
Bug 4290389
Change-Id: I778bc25dcd7e4fa96f003882e34e38fe5aaf40e7
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2992336
(cherry picked from commit a011a22ad5)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3002425
Reviewed-by: Gautham Srinivasan <gauthams@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
159 lines
3.2 KiB
Devicetree
159 lines
3.2 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include "tegra234-p3701-0000-prod-overlay.dtsi"
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/ {
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#ifndef REMOVE_FRAGMENT_SYNTAX
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fragment-t234-p3701-0000@0 {
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target-path = "/";
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__overlay__ {
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#endif
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bus@0 {
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i2c@c240000 {
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ina3221@40 {
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compatible = "ti,ina3221";
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reg = <0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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#io-channel-cells = <1>;
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channel@0 {
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reg = <0x0>;
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label = "VDD_GPU_SOC";
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shunt-resistor-micro-ohms = <2000>;
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};
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channel@1 {
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reg = <0x1>;
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label = "VDD_CPU_CV";
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shunt-resistor-micro-ohms = <2000>;
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};
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channel@2 {
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reg = <0x2>;
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label = "VIN_SYS_5V0";
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shunt-resistor-micro-ohms = <2000>;
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summation-bypass;
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};
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};
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ina3221@41 {
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compatible = "ti,ina3221";
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reg = <0x41>;
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#address-cells = <1>;
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#size-cells = <0>;
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#io-channel-cells = <1>;
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channel@0 {
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reg = <0x0>;
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status = "disabled";
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};
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channel@1 {
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reg = <0x1>;
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label = "VDDQ_VDD2_1V8AO";
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shunt-resistor-micro-ohms = <2000>;
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};
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channel@2 {
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reg = <0x2>;
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status = "disabled";
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};
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};
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};
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spi@3270000 {
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flash@0 {
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spi-max-frequency = <51000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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};
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};
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nvrng@3ae0000 {
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status = "okay";
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};
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};
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hdr40_vdd_3v3: regulator@3 {
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compatible = "regulator-fixed";
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reg = <3>;
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regulator-name = "vdd-3v3-sys";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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bpmp {
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i2c {
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vrs@3c {
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compatible = "nvidia,vrs-pseq";
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reg = <0x3c>;
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interrupt-parent = <&pmc>;
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/* VRS Wake ID is 24 */
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interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "okay";
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};
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tegra_tmp451: thermal-sensor@4c {
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compatible = "ti,tmp451";
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reg = <0x4c>;
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vcc-supply = <&vdd_1v8_ao>;
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#thermal-sensor-cells = <1>;
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status = "okay";
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};
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vrs11_1@20 {
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compatible = "nvidia,vrs11";
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reg = <0x20>;
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rail-name-loopA = "GPU";
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rail-name-loopB = "CPU";
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};
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vrs11_2@22 {
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compatible = "nvidia,vrs11";
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reg = <0x22>;
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rail-name-loopA = "SOC";
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rail-name-loopB = "CV";
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};
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};
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};
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thermal-zones {
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tboard-thermal {
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polling-delay = <1000>;
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polling-delay-passive = <1000>;
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thermal-sensors = <&tegra_tmp451 0>;
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status = "okay";
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};
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tdiode-thermal {
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polling-delay = <1000>;
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polling-delay-passive = <1000>;
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thermal-sensors = <&tegra_tmp451 1>;
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status = "okay";
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};
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};
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eeprom-manager {
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bus@0 {
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i2c-bus = <&gen1_i2c>;
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eeprom@0 {
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slave-address = <0x50>;
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label = "cvm";
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};
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};
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};
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reserved-memory {
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linux,cma { /* Needed for nvgpu comptags */
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x10000000>; /* 256MB */
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alignment = <0x0 0x10000>;
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linux,cma-default;
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status = "okay";
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};
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};
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#ifndef REMOVE_FRAGMENT_SYNTAX
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};
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};
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#endif
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};
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