mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
782ead6230
As part of the process to transitioning to a full featured
base dtb, we need the ability to include various files without
completely rewriting them. This will be an incremental step.
Eventually these preprocessor commands will be removed and
the indentation fixed.
This change is not intended to change any behavior. It is merely
adding the infrastructure for future patches. It will be possible
for a base dts file to define REMOVE_FRAGMENT_SYNTAX and directly
include these files.
Bug 4290389
Change-Id: I778bc25dcd7e4fa96f003882e34e38fe5aaf40e7
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2992336
(cherry picked from commit a011a22ad5)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3002425
Reviewed-by: Gautham Srinivasan <gauthams@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
88 lines
1.9 KiB
Devicetree
88 lines
1.9 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include <dt-bindings/gpio/tegra234-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt/tegra234-irq.h>
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/ {
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#ifndef REMOVE_FRAGMENT_SYNTAX
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p3767-0000-fragment@0 {
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target-path = "/";
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__overlay__ {
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#endif
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bus@0 {
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mmc@3400000 {
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no-sdio;
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no-mmc;
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nvidia,cd-wakeup-capable;
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nvidia,boot-detect-delay = <1000>;
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cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
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};
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nvrng@3ae0000 {
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status = "okay";
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};
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gpu@17000000 {
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status = "okay";
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};
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};
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chosen {
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nvidia,tegra-joint_xpu_rail;
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};
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opp-table-cluster0 {
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opp-1510400000 { /* Max CPU freq for Orin Nano */
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opp-hz = /bits/ 64 <1510400000>;
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opp-peak-kBps = <3200000>;
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};
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opp-1984000000 { /* Max CPU freq for ONX */
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opp-hz = /bits/ 64 <1984000000>;
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opp-peak-kBps = <3200000>;
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};
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};
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opp-table-cluster1 {
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opp-1510400000 { /* Max CPU freq for Orin Nano */
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opp-hz = /bits/ 64 <1510400000>;
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opp-peak-kBps = <3200000>;
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};
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opp-1984000000 { /* Max CPU freq for ONX */
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opp-hz = /bits/ 64 <1984000000>;
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opp-peak-kBps = <3200000>;
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};
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};
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opp-table-cluster2 {
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opp-1510400000 { /* Max CPU freq for Orin Nano */
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opp-hz = /bits/ 64 <1510400000>;
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opp-peak-kBps = <3200000>;
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};
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opp-1984000000 { /* Max CPU freq for ONX */
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opp-hz = /bits/ 64 <1984000000>;
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opp-peak-kBps = <3200000>;
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};
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};
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reserved-memory {
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linux,cma { /* Needed for nvgpu comptags */
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x10000000>; /* 256MB */
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alignment = <0x0 0x10000>;
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linux,cma-default;
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status = "okay";
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};
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};
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#ifndef REMOVE_FRAGMENT_SYNTAX
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};
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};
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#endif
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};
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