mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
af4c57cd95
This is an incremental step toward having a "with-oot" base dtb that contains both the upstream dtb as well as the nvidia-oot data in a single statically built dtb. Note that currently the base dtb is stored and managed in the rootfs via extlinux.conf file. The overlays however live inside the UEFI partition. The ultimate goal is to have consistency in how the dtb files are managed. After we combine the data from nvidia-oot overlay dtb into the future "with-oot" base dtb then we can move the remaining overlays to the rootfs and manage all dtbs/overlays there. This patch takes the first critical step toward this goal by separating the static overlay data from the dynamic overlay data that gets applied conditionally at run-time. Bug 4290389 Change-Id: I403ac84b0737368b8bc96952552729ab7e46802b Signed-off-by: Brad Griffis <bgriffis@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2991524 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
131 lines
3.0 KiB
Devicetree
131 lines
3.0 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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/ {
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fragment-t234-p3737-0000@0 {
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target-path = "/";
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__overlay__ {
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bus@0 {
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spi@3210000{ /* SPI1 in 40 pin conn */
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spi@0 { /* chip select 0 */
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compatible = "tegra-spidev";
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reg = <0x0>;
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spi-max-frequency = <50000000>;
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};
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spi@1 { /* chips select 1 */
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compatible = "tegra-spidev";
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reg = <0x1>;
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spi-max-frequency = <50000000>;
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};
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};
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spi@3230000{ /* SPI3 in 40 pin conn */
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spi@0 { /* chip select 0 */
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compatible = "tegra-spidev";
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reg = <0x0>;
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spi-max-frequency = <50000000>;
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};
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spi@1 { /* chips select 1 */
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compatible = "tegra-spidev";
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reg = <0x1>;
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spi-max-frequency = <50000000>;
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};
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};
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padctl@3520000 {
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ports {
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usb2-0 {
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mode = "otg";
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usb-role-switch;
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};
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};
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};
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aconnect@2900000 {
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ahub@2900800 {
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i2s@2901100 {
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ports {
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port@1 {
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hdr40_snd_i2s_dap_ep: endpoint {
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};
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};
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};
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};
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};
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};
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ethernet@6800000 {
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nvidia,mac-addr-idx = <0>;
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nvidia,max-platform-mtu = <16383>;
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/* 1=enable, 0=disable */
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nvidia,pause_frames = <1>;
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phy-handle = <&mgbe0_aqr113c_phy>;
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phy-mode = "10gbase-r";
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/* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */
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nvidia,phy-iface-mode = <0>;
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nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(Y, 1) 0>;
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nvidia,mdio_addr = <0>;
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mdio {
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compatible = "nvidia,eqos-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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mgbe0_aqr113c_phy: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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nvidia,phy-rst-pdelay-msec = <150>; /* msec */
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nvidia,phy-rst-duration-usec = <221000>; /* usec */
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA234_MAIN_GPIO(Y, 3) IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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};
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tegra_sound_graph: tegra_sound: sound {
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compatible = "nvidia,tegra186-audio-graph-card",
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"nvidia,tegra186-ape";
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clocks = <&bpmp TEGRA234_CLK_PLLA>,
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<&bpmp TEGRA234_CLK_PLLA_OUT0>,
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<&bpmp TEGRA234_CLK_AUD_MCLK>;
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clock-names = "pll_a", "plla_out0", "extern1";
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assigned-clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
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assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
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nvidia-audio-card,name = "NVIDIA Jetson AGX Orin APE";
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nvidia-audio-card,mclk-fs = <256>;
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hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { };
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};
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eeprom-manager {
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data-size = <0x100>;
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bus@0 {
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i2c-bus = <&gen1_i2c>;
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eeprom@1 {
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slave-address = <0x56>;
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label = "cvb";
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};
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};
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bus@1 {
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i2c-bus = <&cam_i2c>;
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eeprom@0 {
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slave-address = <0x54>;
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label = "sensor0";
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};
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eeprom@1 {
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slave-address = <0x57>;
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label = "sensor1";
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};
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eeprom@2 {
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slave-address = <0x52>;
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label = "sensor2";
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};
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};
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};
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};
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};
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};
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