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git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
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b75727c664
Previously soctherm sensors were included in platform-level (cvm+cvb) files. This change moves them to module-level files, since the settings are module-specific. Bug 4893772 Signed-off-by: Yi-Wei Wang <yiweiw@nvidia.com> Change-Id: I3b52dbc6f3183ef18087921cc2782f46d3229fa0 Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3226551 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
65 lines
1.4 KiB
Devicetree
65 lines
1.4 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include "tegra234-p3701-0000-prod-overlay.dtsi"
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#include "nv-soc/tegra234-soc-thermal.dtsi"
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#include "nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi"
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#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
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#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
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/ {
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bpmp {
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i2c {
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vrs@3c {
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compatible = "nvidia,vrs-pseq";
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reg = <0x3c>;
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interrupt-parent = <&pmc>;
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/* VRS Wake ID is 24 */
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interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "okay";
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};
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tegra_tmp451: thermal-sensor@4c {
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#thermal-sensor-cells = <1>;
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};
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vrs11_1@20 {
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compatible = "nvidia,vrs11";
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reg = <0x20>;
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rail-name-loopA = "GPU";
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rail-name-loopB = "CPU";
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};
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vrs11_2@22 {
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compatible = "nvidia,vrs11";
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reg = <0x22>;
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rail-name-loopA = "SOC";
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rail-name-loopB = "CV";
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};
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};
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};
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eeprom-manager {
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bus@0 {
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i2c-bus = <&gen1_i2c>;
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eeprom@0 {
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slave-address = <0x50>;
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label = "cvm";
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};
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};
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};
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reserved-memory {
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linux,cma { /* Needed for nvgpu comptags */
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x10000000>; /* 256MB */
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alignment = <0x0 0x10000>;
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linux,cma-default;
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status = "okay";
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};
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};
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};
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