mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
b75727c664
Previously soctherm sensors were included in platform-level (cvm+cvb) files. This change moves them to module-level files, since the settings are module-specific. Bug 4893772 Signed-off-by: Yi-Wei Wang <yiweiw@nvidia.com> Change-Id: I3b52dbc6f3183ef18087921cc2782f46d3229fa0 Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3226551 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
96 lines
2.3 KiB
Devicetree
96 lines
2.3 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include <dt-bindings/gpio/tegra234-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt/tegra234-irq.h>
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#include "nv-soc/tegra234-soc-thermal.dtsi"
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#include "nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi"
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#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
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#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
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/ {
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bus@0 {
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mmc@3400000 {
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no-sdio;
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no-mmc;
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nvidia,cd-wakeup-capable;
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nvidia,boot-detect-delay = <1000>;
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vmmc-supply = <&vdd_3v3_sd>;
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};
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gpu@17000000 {
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status = "okay";
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};
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};
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chosen {
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nvidia,tegra-joint_xpu_rail;
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};
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opp-table-cluster0 {
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opp-1510400000 { /* Max CPU freq for Orin Nano */
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opp-hz = /bits/ 64 <1510400000>;
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opp-peak-kBps = <3200000>;
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};
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opp-1984000000 { /* Max CPU freq for ONX */
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opp-hz = /bits/ 64 <1984000000>;
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opp-peak-kBps = <3200000>;
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};
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};
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opp-table-cluster1 {
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opp-1510400000 { /* Max CPU freq for Orin Nano */
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opp-hz = /bits/ 64 <1510400000>;
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opp-peak-kBps = <3200000>;
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};
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opp-1984000000 { /* Max CPU freq for ONX */
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opp-hz = /bits/ 64 <1984000000>;
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opp-peak-kBps = <3200000>;
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};
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};
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opp-table-cluster2 {
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opp-1510400000 { /* Max CPU freq for Orin Nano */
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opp-hz = /bits/ 64 <1510400000>;
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opp-peak-kBps = <3200000>;
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};
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opp-1984000000 { /* Max CPU freq for ONX */
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opp-hz = /bits/ 64 <1984000000>;
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opp-peak-kBps = <3200000>;
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};
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};
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reserved-memory {
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linux,cma { /* Needed for nvgpu comptags */
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x10000000>; /* 256MB */
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alignment = <0x0 0x10000>;
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linux,cma-default;
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status = "okay";
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};
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};
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vdd_3v3_sd: regulator-vdd-3v3-sd {
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compatible = "regulator-fixed";
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regulator-name = "VDD_3V3_SD";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio TEGRA234_MAIN_GPIO(A, 0) GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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hdr40_vdd_3v3: regulator-vdd-3v3-sys {
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/* BUCK_3V3_EN enable is driven by button MCU */
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compatible = "regulator-fixed";
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regulator-name = "VDD-3V3-SYS";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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