mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
- Upstream DT only enables the IO ports which are exposed out of CVB.
- Remove unnecessary IO nodes from downstream DT.
- Removed nodes are :
agx/concord(p3737) : I2S3, I2S5, DMIC1, DMIC2, DMIC4, DSPK1, DSPK2
igx(p3740) : I2S3, I2S5, DMIC1, DMIC2, DMIC4, DSPK1, DSPK2
nano/nx (p3768) : I2S1, I2S3, I2S5, DMIC1, DMIC2, DMIC3, DMIC4,
DSPK1, DSPK2
Bug 4961348
Change-Id: Id493ae743446d888fe322dd3887729376555541f
Signed-off-by: Ritu Chaudhary <rituc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3263289
Reviewed-by: Mohan kumar <mkumard@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Sheetal . <sheetal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
296 lines
4.6 KiB
Devicetree
296 lines
4.6 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#include "nv-soc/tegra234-overlay.dtsi"
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#include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
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#include "tegra234-p3768-0000.dtsi"
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#include "tegra234-p3767-0000.dtsi"
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#include "nv-soc/tegra234-soc-camera.dtsi"
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#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
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/ {
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aliases {
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serial1 = &uarta;
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serial2 = &uarte;
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};
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bpmp {
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i2c {
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vrs@3c {
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compatible = "nvidia,vrs-pseq";
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reg = <0x3c>;
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interrupt-parent = <&pmc>;
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/* VRS Wake ID is 24 */
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interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "okay";
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};
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};
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};
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bus@0 {
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actmon@d230000 {
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status = "okay";
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};
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pinmux@2430000 {
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status = "okay";
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};
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i2c@3180000 {
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status = "okay";
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};
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aconnect@2900000 {
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adsp@2993000 {
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status = "okay";
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};
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};
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i2c@31b0000 {
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status = "okay";
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};
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hdr40_i2c1: i2c@c250000 {
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status = "okay";
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};
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/* SPI1, 40pin header, Pin 19(MOSI), Pin 21(MISO), Pin 23(CLK), Pin 24(CS) */
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spi@3210000{
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status = "okay";
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spi@0 {
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compatible = "tegra-spidev";
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reg = <0x0>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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spi@1 {
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compatible = "tegra-spidev";
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reg = <0x1>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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};
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/* SPI3, 40pin header, Pin 37(MOSI), Pin 22(MISO), Pin 13(CLK), Pin 18(CS) */
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spi@3230000{
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status = "okay";
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spi@0 {
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compatible = "tegra-spidev";
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reg = <0x0>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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spi@1 {
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compatible = "tegra-spidev";
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reg = <0x1>;
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spi-max-frequency = <50000000>;
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controller-data {
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x10>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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};
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padctl@3520000 {
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ports {
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usb2-0 {
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port {
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typec_p0: endpoint {
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remote-endpoint = <&fusb_p0>;
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};
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};
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};
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};
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};
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i2c@c240000 {
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status = "okay";
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fusb301@25 {
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compatible = "onsemi,fusb301";
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reg = <0x25>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&gpio>;
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interrupts = <TEGRA234_MAIN_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>;
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connector@0 {
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port@0 {
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fusb_p0: endpoint {
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remote-endpoint = <&typec_p0>;
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};
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};
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};
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};
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};
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/* PWM1, 40pin header, pin 15 */
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pwm@3280000 {
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status = "okay";
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};
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/* PWM3, FAN */
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pwm@32a0000 {
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status = "okay";
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};
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/* PWM5, 40pin header, pin 33 */
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pwm@32c0000 {
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status = "okay";
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};
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/* PWM7, 40pin header, pin 32 */
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pwm@32e0000 {
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status = "okay";
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};
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tachometer@39c0000 {
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status = "okay";
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upper-threshold = <0xfffff>;
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lower-threshold = <0x0>;
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};
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hsp@3d00000 {
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status = "okay";
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};
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aon@c000000 {
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status = "okay";
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};
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hardware-timestamp@c1e0000 {
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status = "okay";
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};
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mttcan@c310000 {
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status = "okay";
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};
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hwpm@f100000 {
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status = "okay";
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};
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mc-hwpm@2c10000 {
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status = "okay";
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};
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host1x@13e00000 {
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nvdec@15480000 {
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status = "okay";
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};
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nvenc@154c0000 {
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status = "okay";
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};
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crypto@15820000 {
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status = "okay";
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};
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crypto@15840000 {
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status = "okay";
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};
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nvdla0@15880000 {
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status = "okay";
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};
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nvdla1@158c0000 {
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status = "okay";
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};
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ofa@15a50000 {
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status = "okay";
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};
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pva0@16000000 {
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status = "okay";
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pva0_niso1_ctx0 {
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status = "okay";
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};
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pva0_niso1_ctx1 {
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status = "okay";
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};
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pva0_niso1_ctx2 {
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status = "okay";
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};
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pva0_niso1_ctx3 {
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status = "okay";
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};
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pva0_niso1_ctx4 {
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status = "okay";
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};
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pva0_niso1_ctx5 {
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status = "okay";
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};
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pva0_niso1_ctx6 {
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status = "okay";
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};
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pva0_niso1_ctx7 {
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status = "okay";
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};
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};
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nvjpg@15380000 {
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status = "okay";
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};
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nvjpg@15540000 {
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status = "okay";
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};
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};
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};
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cpus {
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idle-states {
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c7 {
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status = "okay";
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};
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};
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};
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nvpmodel {
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status = "okay";
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};
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soctherm-oc-event {
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status = "okay";
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};
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tegra-hsp@b950000 {
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status = "okay";
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};
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dce@d800000 {
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status = "okay";
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};
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display@13800000 {
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status = "okay";
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};
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};
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/delete-node/ &{/gpio-keys/key-suspend};
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