mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git
synced 2025-12-22 09:12:02 +03:00
ed0ab24f08
Made following changes: 1.Add 4xHawk & 4xOwl module support on P3762 & P3783. 2.Fix simultaneous streaming of Owl & Hawk. 3.Update EEPROM address for Hawk & Owl. 4.Add DT support for TSC gen. 5.Add virtual i2c mux node for p3762. 6.Add overlay support for P3762 & P3783. Bug 3620984 Bug 3562348 Bug 3866131 Bug 3932004 Bug 4096788 Bug 4091221 Bug 4146784 Bug 4245526 Change-Id: I15d731249234711c706c2fb8f6a3cfc1d9fc125d Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2971173 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
289 lines
9.7 KiB
Devicetree
289 lines
9.7 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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/dts-v1/;
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/plugin/;
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#include "tegra234-camera-p3783-a00.dtsi"
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#include "dt-bindings/gpio/tegra234-gpio.h"
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#include "dt-bindings/clock/tegra234-clock.h"
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#define CAM0_RST_L TEGRA234_MAIN_GPIO(H, 3)
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#define CAM0_PWDN TEGRA234_MAIN_GPIO(H, 6)
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#define CAM1_RST_L TEGRA234_MAIN_GPIO(AC, 1)
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#define CAM1_PWDN TEGRA234_MAIN_GPIO(AC, 0)
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#define PWR_EN TEGRA234_MAIN_GPIO(AC, 7)
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#define GYRO1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 1)
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#define ACCE1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 0)
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#define CAMERA_I2C_MUX_BUS(x) (0x1E + x)
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/* camera control gpio definitions */
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/ {
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overlay-name = "Jetson Camera Hawk-Owl p3783 module";
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jetson-header-name = "Jetson 122pin CSI Connector";
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compatible = "nvidia,p3740-0000+p3701-0000", "nvidia,p3740-0002-b01+p3701-0002","nvidia,p3740-0002+p3701-0008";
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fragment-camera-hawk-owl@0 {
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target-path = "/";
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__overlay__ {
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bus@0 {
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/* set camera gpio direction to output */
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gpio@2200000 {
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camera-control-output-low {
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gpio-hog;
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output-low;
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gpios = <CAM0_RST_L 0 CAM0_PWDN 0
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CAM1_RST_L 0 CAM1_PWDN 0>;
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label = "cam0-rst", "cam0-pwdn",
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"cam1-rst", "cam1-pwdn";
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};
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};
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i2c@3180000 {
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max96712_b@62 {
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compatible = "nvidia,max96712";
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reg = <0x62>;
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channel = "b";
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pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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ar0234_i@30 {
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status = "okay";
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def-addr = <0x18>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "b";
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has-eeprom;
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eeprom-addr = <0x38>;
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reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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ar0234_j@32 {
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status = "okay";
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def-addr = <0x18>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "b";
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has-eeprom;
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eeprom-addr = <0x3a>;
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reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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ar0234_k@34 {
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status = "okay";
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def-addr = <0x18>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "b";
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has-eeprom;
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eeprom-addr = <0x3c>;
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reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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ar0234_l@36 {
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status = "okay";
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def-addr = <0x18>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "b";
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has-eeprom;
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eeprom-addr = <0x3e>;
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reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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};
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i2c@31e0000 {
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max96712_a@62 {
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compatible = "nvidia,max96712";
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reg = <0x62>;
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channel = "a";
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pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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virtual_i2c_mux@50 {
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reg = <0x50>;
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compatible = "nvidia,virtual-i2c-mux";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&dp_aux_ch3_i2c>;
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status = "okay";
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i2c@0 {
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reg = <0>;
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i2c-mux,deselect-on-exit;
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#address-cells = <1>;
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#size-cells = <0>;
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bmi088_a@69 {
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compatible = "bmi,bmi088";
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reg = <0x69>;
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accel_i2c_addr = <0x19>;
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accel_irq_gpio = <&gpio_aon ACCE1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
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gyro_irq_gpio = <&gpio_aon GYRO1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
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accel_matrix = [01 00 00 00 01 00 00 00 01];
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gyro_matrix = [01 00 00 00 01 00 00 00 01];
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gyro_reg_0x18 = <0x81>;
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status = "okay";
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};
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ar0234_a@30 {
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status = "okay";
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def-addr = <0x10>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "a";
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has-eeprom;
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eeprom-addr = <0x40>;
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reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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ar0234_b@31 {
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status = "okay";
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def-addr = <0x18>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "c";
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has-eeprom;
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eeprom-addr = <0x40>;
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reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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};
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i2c@1 {
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reg = <1>;
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i2c-mux,deselect-on-exit;
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#address-cells = <1>;
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#size-cells = <0>;
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ar0234_c@32 {
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status = "okay";
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def-addr = <0x10>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "a";
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has-eeprom;
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eeprom-addr = <0x42>;
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reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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ar0234_d@33 {
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status = "okay";
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def-addr = <0x18>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "c";
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has-eeprom;
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eeprom-addr = <0x42>;
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reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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ar0234_e@34 {
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status = "okay";
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def-addr = <0x10>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "a";
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has-eeprom;
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eeprom-addr = <0x44>;
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reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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ar0234_f@35 {
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status = "okay";
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def-addr = <0x18>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "c";
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has-eeprom;
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eeprom-addr = <0x44>;
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reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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ar0234_g@36 {
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status = "okay";
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def-addr = <0x10>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "a";
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has-eeprom;
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eeprom-addr = <0x46>;
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reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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ar0234_h@37 {
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status = "okay";
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def-addr = <0x18>;
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/* Define any required hw resources needed by driver */
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/* ie. clocks, io pins, power sources */
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clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
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<&bpmp TEGRA234_CLK_EXTPERIPH1>;
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clock-names = "extperiph1", "pllp_grtba";
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mclk = "extperiph1";
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channel = "c";
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has-eeprom;
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eeprom-addr = <0x46>;
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reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
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pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
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pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
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};
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};
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};
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};
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};
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};
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};
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};
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