From 020a01a6208f5b0613fd8094d446a25e6f0890bb Mon Sep 17 00:00:00 2001 From: Jonathan Hunter Date: Wed, 11 Sep 2019 14:46:01 +0100 Subject: [PATCH] common: overlay: Add common overlay for Jetson Add the following device-tree overlay templates for the Jetson platforms. 1. ADAFRUIT SPH0645LM4H (I2S MEMS Microphone) 2. FE-PI Audio Z V2 (SGTL5000 Audio Codec) Note that these templates cannot be compiled as-is because they include definitions that are defined in the corresponding 'dt-bindings/platform/jetson/.h'. Therefore, to use these templates they need to be compiled along with the appropriate include file. These have been created to avoid duplicating nodes that are common to all Jetson platforms for using these add-on modules. Bug 2414131 Change-Id: I60b29bb72fdd206786fd76cd1676ed6d6f3c9f1b Signed-off-by: Jonathan Hunter Reviewed-on: https://git-master.nvidia.com/r/2202471 (cherry picked from commit 3ca13ed86364fe2b606e470870ffa778f36a03c9) Reviewed-on: https://git-master.nvidia.com/r/2217432 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu Tested-by: Bibek Basu Reviewed-by: mobile promotions Tested-by: mobile promotions --- overlay/jetson-adafruit-sph0645lm4h.dtsi | 49 ++++++++++ overlay/jetson-fe-pi-audio-z-v2.dts | 110 +++++++++++++++++++++++ 2 files changed, 159 insertions(+) create mode 100644 overlay/jetson-adafruit-sph0645lm4h.dtsi create mode 100644 overlay/jetson-fe-pi-audio-z-v2.dts diff --git a/overlay/jetson-adafruit-sph0645lm4h.dtsi b/overlay/jetson-adafruit-sph0645lm4h.dtsi new file mode 100644 index 0000000..ae9e832 --- /dev/null +++ b/overlay/jetson-adafruit-sph0645lm4h.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Jetson Device-tree overlay for Adafruit I2S MEMS Microphone Breakout + * (SPH0645LM4H). + * + * Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved. + * + */ + +#include + +/ { + overlay-name = "Adafruit SPH0645LM4H"; + compatible = JETSON_COMPATIBLE; + + fragment@0 { + target = <&pinmux>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&hdr40_pinmux>; + + hdr40_pinmux: header-40pin-pinmux { + pin12 { + nvidia,pins = HDR40_PIN12; + nvidia,function = HDR40_I2S; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pin35 { + nvidia,pins = HDR40_PIN35; + nvidia,function = HDR40_I2S; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pin38 { + nvidia,pins = HDR40_PIN38; + nvidia,function = HDR40_I2S; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + }; +}; diff --git a/overlay/jetson-fe-pi-audio-z-v2.dts b/overlay/jetson-fe-pi-audio-z-v2.dts new file mode 100644 index 0000000..42b579f --- /dev/null +++ b/overlay/jetson-fe-pi-audio-z-v2.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Jetson Device-tree overlay for FE-PI Audio Z V2. + * + * Copyright (c) 2019 NVIDIA CORPORATION. All rights reserved. + * + */ + +#include + +/ { + overlay-name = "FE-PI Audio Z V2"; + compatible = JETSON_COMPATIBLE; + + fragment@0 { + target-path = "/"; + __overlay__ { + clocks { + sgtl5000_mclk: sgtl5000_mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "sgtl5000-mclk"; + status = "okay"; + }; + }; + }; + }; + + fragment@1 { + target = <&hdr40_i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sgtl5000_mclk>; + micbias-resistor-k-ohms = <2>; + micbias-voltage-m-volts = <3000>; + VDDA-supply = <&hdr40_vdd_3v3>; + VDDIO-supply = <&hdr40_vdd_3v3>; + status = "okay"; + }; + }; + }; + + fragment@2 { + target = <&tegra_sound>; + __overlay__ { + nvidia,audio-routing = + "x Headphone", "x HP_OUT", + "x MIC_IN", "x Mic"; + }; + }; + + fragment@3 { + target = <&hdr40_snd_link_i2s>; + __overlay__ { + link-name = "fe-pi-audio-z-v2"; + codec-dai = <&sgtl5000>; + codec-dai-name = "sgtl5000"; + bitclock-master; + frame-master; + }; + }; + + fragment@4 { + target = <&pinmux>; + __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&hdr40_pinmux>; + + hdr40_pinmux: header-40pin-pinmux { + pin12 { + nvidia,pins = HDR40_PIN12; + nvidia,function = HDR40_I2S; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pin35 { + nvidia,pins = HDR40_PIN35; + nvidia,function = HDR40_I2S; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pin38 { + nvidia,pins = HDR40_PIN38; + nvidia,function = HDR40_I2S; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + pin40 { + nvidia,pins = HDR40_PIN40; + nvidia,function = HDR40_I2S; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + }; +};