From 35bbd98521f2787d28e50e321de2fc2265092a8f Mon Sep 17 00:00:00 2001 From: Joseph Yoon Date: Fri, 14 Jun 2024 20:08:50 +0800 Subject: [PATCH] t234: nv-public: Add HSP shared IRQ decl macro Add HSP shared IRQ declaration macro Jira ESQCD60-9998 Change-Id: Ibc98e89d018bb62d0c04c18b221978b8480e0e0b Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3157444 Tested-by: Jinyoung Park GVS: buildbot_gerritrpt Reviewed-by: Laxman Dewangan Reviewed-by: Joseph Yoon Reviewed-by: Hyong Bin Kim Tested-by: Joseph Yoon Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/tegra-public-dts/+/3171453 Tested-by: Laxman Dewangan --- .../dt-bindings/mailbox/tegra186-hsp-oot.h | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 include/nvidia-oot/dt-bindings/mailbox/tegra186-hsp-oot.h diff --git a/include/nvidia-oot/dt-bindings/mailbox/tegra186-hsp-oot.h b/include/nvidia-oot/dt-bindings/mailbox/tegra186-hsp-oot.h new file mode 100644 index 0000000..4434bdb --- /dev/null +++ b/include/nvidia-oot/dt-bindings/mailbox/tegra186-hsp-oot.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for binding nvidia,tegra186-hsp. + */ + +#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_OOT_H +#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_OOT_H + +#include + +/* + * These define the types of shared mailbox supported based on data size. + */ +#ifdef TEGRA_HSP_MBOX_TYPE_SM_128BIT +#undef TEGRA_HSP_MBOX_TYPE_SM_128BIT +#endif + +#define TEGRA_HSP_MBOX_TYPE_SM_128BIT 0x4 + +/* + * Shared interrupt source, mapped with mailboxes + */ +#define TEGRA_HSP_SHARED_IRQ_MASK 0xffff0000 +#define TEGRA_HSP_SHARED_IRQ_OFFSET (16) +#define TEGRA_HSP_SHARED_IRQ(x) (((x) << TEGRA_HSP_SHARED_IRQ_OFFSET) & TEGRA_HSP_SHARED_IRQ_MASK) + +#endif