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common: overlay: Add MCP251x overlay

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Adding MCP251x overlay dts file which is made common to be used on
all jetson platforms.

Bug 2733928

Change-Id: I3d1bf5dd2307a2039a38d1d5ae9db58a74755f88
Signed-off-by: Shubhi Garg <shgarg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/platform/tegra/common/+/2326443
(cherry picked from commit c6592f3ab2277110a4b744e605a167b7e3170cbc)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/platform/tegra/common/+/2356320
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Shubhi Garg
2020-04-09 13:58:29 +05:30
committed by Laxman Dewangan
parent 9341e77759
commit 8dd941ec2f
1 changed files with 96 additions and 0 deletions
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96
overlay/jetson-mcp251x.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Jetson Device-tree overlay for MCP251x CAN Controller.
*
* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved.
*
*/
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
/ {
overlay-name = "MCP251x CAN Controller";
compatible = JETSON_COMPATIBLE;
fragment@0 {
target-path = "/";
__overlay__ {
clocks {
can_clock: can_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <20000000>;
clock-accuracy = <100>;
};
};
};
};
fragment@1 {
target = <&hdr40_spi1>;
__overlay__ {
spi@0 {
compatible = "microchip,mcp2515";
reg = <0x0>;
spi-max-frequency = <10000000>;
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x7>;
clocks = <&can_clock>;
interrupt-parent = <&gpio>;
interrupts = <HDR40_PIN31_GPIO 0x1>;
controller-data {
nvidia,cs-setup-clk-count = <0x1e>;
nvidia,cs-hold-clk-count = <0x1e>;
nvidia,rx-clk-tap-delay = <0x1f>;
nvidia,tx-clk-tap-delay = <0x0>;
};
};
};
};
fragment@2 {
target = <&pinmux>;
__overlay__ {
pinctrl-names = "default";
pinctrl-0 = <&hdr40_pinmux>;
hdr40_pinmux: header-40pin-pinmux {
pin19 {
nvidia,pins = HDR40_PIN19;
nvidia,function = HDR40_SPI;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pin21 {
nvidia,pins = HDR40_PIN21;
nvidia,function = HDR40_SPI;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pin23 {
nvidia,pins = HDR40_PIN23;
nvidia,function = HDR40_SPI;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pin24 {
nvidia,pins = HDR40_PIN24;
nvidia,function = HDR40_SPI;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pin26 {
nvidia,pins = HDR40_PIN26;
nvidia,function = HDR40_SPI;
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
};
};
};