From 8fdbcfc7ff57c35f9ae7bdedb2d5949b4ea830cb Mon Sep 17 00:00:00 2001 From: Lovie Wang Date: Mon, 11 Sep 2023 12:48:39 +0800 Subject: [PATCH] t23x: overlay: fsicom: add new hsp mailbox and stream id inst - add top2 hsp mailbox 5 and 4 for core 1 usage - add FSI_CPU1 stream id for core 1 memory map - newnode created for each SMMU inst Bug 4243457 Change-Id: Id66c060d5daa1ca6458e3cbeee81dafc88904560 Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2977860 Reviewed-by: Prashant Kumar Shaw Reviewed-by: Laxman Dewangan GVS: Gerrit_Virtual_Submit Tested-by: Lovie Wang Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/tegra-public-dts/+/3168934 Tested-by: Laxman Dewangan GVS: buildbot_gerritrpt --- include/kernel/dt-bindings/memory/tegra234-mc.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/kernel/dt-bindings/memory/tegra234-mc.h b/include/kernel/dt-bindings/memory/tegra234-mc.h index 6e60d55..ad7b575 100644 --- a/include/kernel/dt-bindings/memory/tegra234-mc.h +++ b/include/kernel/dt-bindings/memory/tegra234-mc.h @@ -114,7 +114,7 @@ #define TEGRA234_SID_XUSB_HOST 0x0e #define TEGRA234_SID_XUSB_DEV 0x0f #define TEGRA234_SID_BPMP 0x10 -#define TEGRA234_SID_FSI 0x11 +#define TEGRA234_SID_NISO1_FSI_CPU0 0x11 #define TEGRA234_SID_PVA0_VM0 0x12 #define TEGRA234_SID_PVA0_VM1 0x13 #define TEGRA234_SID_PVA0_VM2 0x14 @@ -171,6 +171,11 @@ #define TEGRA234_SID_HOST1X_CTX6 0x3b #define TEGRA234_SID_HOST1X_CTX7 0x3c +/*FSI Stream Id*/ +#define TEGRA234_SID_NISO1_FSI_CPU1 0x4BU +#define TEGRA234_SID_NISO1_FSI_CPU2 0x4CU +#define TEGRA234_SID_NISO1_FSI_CPU3 0X4DU + /* * memory client IDs */