mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/tegra-public-dts.git
synced 2025-12-22 09:11:55 +03:00
0494ee2972
- change all dt file licenses to Nvidia, Nvidia Copyright, GPLv2 License - GPLv2 License: https://wiki.nvidia.com/nvwiki/index.php/SW_IP_Audit_Team/Licenses/GPLv2-only ESLC-5105 Change-Id: I069e525ebb521b986156495ec1c791f5a97a8b39 Signed-off-by: Ronit Halder <rhalder@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/platform/tegra/common/+/2383708 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vipin Kumar <vipink@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
109 lines
2.8 KiB
Devicetree
109 lines
2.8 KiB
Devicetree
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Jetson Device-tree overlay for MCP251x CAN Controller.
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*/
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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/ {
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overlay-name = "MCP251x CAN Controller";
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compatible = JETSON_COMPATIBLE;
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fragment@0 {
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target-path = "/";
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__overlay__ {
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clocks {
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can_clock: can_clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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clock-accuracy = <100>;
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};
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};
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};
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};
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fragment@1 {
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target = <&hdr40_spi1>;
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__overlay__ {
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spi@0 {
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compatible = "microchip,mcp2515";
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reg = <0x0>;
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spi-max-frequency = <10000000>;
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nvidia,enable-hw-based-cs;
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nvidia,rx-clk-tap-delay = <0x7>;
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clocks = <&can_clock>;
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interrupt-parent = <&gpio>;
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interrupts = <HDR40_PIN31_GPIO 0x1>;
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controller-data {
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nvidia,cs-setup-clk-count = <0x1e>;
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nvidia,cs-hold-clk-count = <0x1e>;
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nvidia,rx-clk-tap-delay = <0x1f>;
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nvidia,tx-clk-tap-delay = <0x0>;
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};
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};
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};
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};
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fragment@2 {
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target = <&pinmux>;
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__overlay__ {
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pinctrl-names = "default";
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pinctrl-0 = <&hdr40_pinmux>;
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hdr40_pinmux: header-40pin-pinmux {
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pin19 {
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nvidia,pins = HDR40_PIN19;
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nvidia,function = HDR40_SPI;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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pin21 {
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nvidia,pins = HDR40_PIN21;
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nvidia,function = HDR40_SPI;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pin23 {
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nvidia,pins = HDR40_PIN23;
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nvidia,function = HDR40_SPI;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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pin24 {
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nvidia,pins = HDR40_PIN24;
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nvidia,function = HDR40_SPI;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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pin26 {
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nvidia,pins = HDR40_PIN26;
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nvidia,function = HDR40_SPI;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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};
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};
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};
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};
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