mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/tegra-public-dts.git
synced 2025-12-22 09:11:55 +03:00
35bbd98521
Add HSP shared IRQ declaration macro Jira ESQCD60-9998 Change-Id: Ibc98e89d018bb62d0c04c18b221978b8480e0e0b Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3157444 Tested-by: Jinyoung Park <jinyoungp@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Joseph Yoon <tyoon@nvidia.com> Reviewed-by: Hyong Bin Kim <hyongbink@nvidia.com> Tested-by: Joseph Yoon <tyoon@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/tegra-public-dts/+/3171453 Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
28 lines
714 B
C
28 lines
714 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* This header provides constants for binding nvidia,tegra186-hsp.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_OOT_H
|
|
#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_OOT_H
|
|
|
|
#include <dt-bindings/mailbox/tegra186-hsp.h>
|
|
|
|
/*
|
|
* These define the types of shared mailbox supported based on data size.
|
|
*/
|
|
#ifdef TEGRA_HSP_MBOX_TYPE_SM_128BIT
|
|
#undef TEGRA_HSP_MBOX_TYPE_SM_128BIT
|
|
#endif
|
|
|
|
#define TEGRA_HSP_MBOX_TYPE_SM_128BIT 0x4
|
|
|
|
/*
|
|
* Shared interrupt source, mapped with mailboxes
|
|
*/
|
|
#define TEGRA_HSP_SHARED_IRQ_MASK 0xffff0000
|
|
#define TEGRA_HSP_SHARED_IRQ_OFFSET (16)
|
|
#define TEGRA_HSP_SHARED_IRQ(x) (((x) << TEGRA_HSP_SHARED_IRQ_OFFSET) & TEGRA_HSP_SHARED_IRQ_MASK)
|
|
|
|
#endif
|