mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/tegra-public-dts.git
synced 2025-12-22 09:11:55 +03:00
550c2456a3
Upstream AHUB drivers have following variations when compared to
OOT versions:
- Upstream AHUB drivers of I/O modules don't expose dummy DAIs.
To use upstream AHUB drivers, legacy machine driver exposes
dummy DAI and use the same here. There were objections from
upstream maintainers to expose dummy DAIs from the I/O module
drivers. Hence these are now exposed from the legacy machine
driver.
- DAI index of ADX input and output ports are different in
upstream ADX driver.
To use upstream ADX driver update the DAI index values.
- Upstream SFC, OPE and MVC drivers use separate ports for
input and output.
To use upstream drivers, use correct DAI index of for these
modules. Remove the TODO comment and cleanup the macro check.
- ARAD, AFC and ADSP audio devices are yet to be upstreamed.
Remove DAI links related to these modules to allow legacy
machine driver to work with already upstreamed AHUB drivers.
There is no plan to productize these modules with legacy
machine driver and hence these can be removed. In future,
these will be supported from graph card driver and the DT
binding for it is going to be different anyways.
Bug 4451662
Bug 4432184
TAS-2251
Change-Id: I934a75c067e46433b41a484bdacaa5e2c66566cb
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3059813
Reviewed-by: Mohan kumar <mkumard@nvidia.com>
Reviewed-by: Sheetal . <sheetal@nvidia.com>
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/tegra-public-dts/+/3171449
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
323 lines
7.3 KiB
C
323 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// SPDX-FileCopyrightText: Copyright (c) 2019-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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#ifndef __DT_TEGRA_ASOC_DAIS_H
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#define __DT_TEGRA_ASOC_DAIS_H
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/*
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* DAI links can have one of these value
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* PCM_LINK : optional, if nothing is specified link is treated as PCM link
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* COMPR_LINK : required, if link is used with compress device
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* C2C_LINK : required, for any other back end codec-to-codec links
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*/
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#define PCM_LINK 0
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#define COMPR_LINK 1
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#define C2C_LINK 2
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/*
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* Following DAI indices are derived from respective module drivers.
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* Thus below values have to be in sync with the DAI arrays defined
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* in the drivers.
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*/
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#define XBAR_ADMAIF1 0
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#define XBAR_ADMAIF2 1
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#define XBAR_ADMAIF3 2
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#define XBAR_ADMAIF4 3
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#define XBAR_ADMAIF5 4
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#define XBAR_ADMAIF6 5
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#define XBAR_ADMAIF7 6
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#define XBAR_ADMAIF8 7
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#define XBAR_ADMAIF9 8
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#define XBAR_ADMAIF10 9
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#define XBAR_ADMAIF11 10
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#define XBAR_ADMAIF12 11
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#define XBAR_ADMAIF13 12
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#define XBAR_ADMAIF14 13
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#define XBAR_ADMAIF15 14
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#define XBAR_ADMAIF16 15
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#define XBAR_ADMAIF17 16
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#define XBAR_ADMAIF18 17
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#define XBAR_ADMAIF19 18
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#define XBAR_ADMAIF20 19
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#define XBAR_I2S1 20
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#define XBAR_I2S2 21
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#define XBAR_I2S3 22
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#define XBAR_I2S4 23
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#define XBAR_I2S5 24
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#define XBAR_I2S6 25
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#define XBAR_DMIC1 26
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#define XBAR_DMIC2 27
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#define XBAR_DMIC3 28
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#define XBAR_DMIC4 29
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#define XBAR_DSPK1 30
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#define XBAR_DSPK2 31
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#define XBAR_SFC1_RX 32
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#define XBAR_SFC1_TX 33
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#define XBAR_SFC2_RX 34
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#define XBAR_SFC2_TX 35
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#define XBAR_SFC3_RX 36
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#define XBAR_SFC3_TX 37
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#define XBAR_SFC4_RX 38
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#define XBAR_SFC4_TX 39
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#define XBAR_MVC1_RX 40
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#define XBAR_MVC1_TX 41
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#define XBAR_MVC2_RX 42
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#define XBAR_MVC2_TX 43
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#define XBAR_AMX1_IN1 44
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#define XBAR_AMX1_IN2 45
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#define XBAR_AMX1_IN3 46
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#define XBAR_AMX1_IN4 47
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#define XBAR_AMX1_OUT 48
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#define XBAR_AMX2_IN1 49
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#define XBAR_AMX2_IN2 50
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#define XBAR_AMX2_IN3 51
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#define XBAR_AMX2_IN4 52
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#define XBAR_AMX2_OUT 53
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#define XBAR_AMX3_IN1 54
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#define XBAR_AMX3_IN2 55
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#define XBAR_AMX3_IN3 56
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#define XBAR_AMX3_IN4 57
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#define XBAR_AMX3_OUT 58
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#define XBAR_AMX4_IN1 59
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#define XBAR_AMX4_IN2 60
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#define XBAR_AMX4_IN3 61
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#define XBAR_AMX4_IN4 62
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#define XBAR_AMX4_OUT 63
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#define XBAR_ADX1_IN 64
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#define XBAR_ADX1_OUT1 65
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#define XBAR_ADX1_OUT2 66
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#define XBAR_ADX1_OUT3 67
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#define XBAR_ADX1_OUT4 68
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#define XBAR_ADX2_IN 69
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#define XBAR_ADX2_OUT1 70
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#define XBAR_ADX2_OUT2 71
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#define XBAR_ADX2_OUT3 72
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#define XBAR_ADX2_OUT4 73
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#define XBAR_ADX3_IN 74
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#define XBAR_ADX3_OUT1 75
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#define XBAR_ADX3_OUT2 76
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#define XBAR_ADX3_OUT3 77
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#define XBAR_ADX3_OUT4 78
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#define XBAR_ADX4_IN 79
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#define XBAR_ADX4_OUT1 80
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#define XBAR_ADX4_OUT2 81
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#define XBAR_ADX4_OUT3 82
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#define XBAR_ADX4_OUT4 83
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#define XBAR_MIXER_IN1 84
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#define XBAR_MIXER_IN2 85
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#define XBAR_MIXER_IN3 86
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#define XBAR_MIXER_IN4 87
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#define XBAR_MIXER_IN5 88
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#define XBAR_MIXER_IN6 89
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#define XBAR_MIXER_IN7 90
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#define XBAR_MIXER_IN8 91
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#define XBAR_MIXER_IN9 92
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#define XBAR_MIXER_IN10 93
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#define XBAR_MIXER_OUT1 94
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#define XBAR_MIXER_OUT2 95
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#define XBAR_MIXER_OUT3 96
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#define XBAR_MIXER_OUT4 97
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#define XBAR_MIXER_OUT5 98
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#define XBAR_ASRC_IN1 99
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#define XBAR_ASRC_OUT1 100
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#define XBAR_ASRC_IN2 101
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#define XBAR_ASRC_OUT2 102
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#define XBAR_ASRC_IN3 103
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#define XBAR_ASRC_OUT3 104
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#define XBAR_ASRC_IN4 105
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#define XBAR_ASRC_OUT4 106
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#define XBAR_ASRC_IN5 107
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#define XBAR_ASRC_OUT5 108
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#define XBAR_ASRC_IN6 109
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#define XBAR_ASRC_OUT6 110
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#define XBAR_ASRC_IN7 111
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#define XBAR_OPE1_RX 112
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#define XBAR_OPE1_TX 113
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#define XBAR_AFC1 114
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#define XBAR_AFC2 115
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#define XBAR_AFC3 116
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#define XBAR_AFC4 117
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#define XBAR_AFC5 118
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#define XBAR_AFC6 119
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#define XBAR_SPKPROT 120
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#define XBAR_IQC1_1 121
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#define XBAR_IQC1_2 122
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#define XBAR_IQC2_1 123
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#define XBAR_IQC2_2 124
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#define XBAR_ARAD 125
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/* ADMAIF DAIs */
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#define ADMAIF1 0
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#define ADMAIF2 1
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#define ADMAIF3 2
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#define ADMAIF4 3
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#define ADMAIF5 4
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#define ADMAIF6 5
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#define ADMAIF7 6
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#define ADMAIF8 7
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#define ADMAIF9 8
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#define ADMAIF10 9
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#define ADMAIF11 10
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#define ADMAIF12 11
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#define ADMAIF13 12
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#define ADMAIF14 13
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#define ADMAIF15 14
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#define ADMAIF16 15
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#define ADMAIF17 16
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#define ADMAIF18 17
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#define ADMAIF19 18
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#define ADMAIF20 19
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/*
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* ADMAIF_FIFO: DAIs used for DAI links between ADMAIF and ADSP.
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* Offset depends on the number of ADMAIF channels for a chip.
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* The DAI indices for these are derived from below offsets.
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*/
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#define TEGRA186_ADMAIF_FIFO_OFFSET 20
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/*
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* ADMAIF_CIF: DAIs used for codec-to-codec links between ADMAIF and XBAR.
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* Offset depends on the number of ADMAIF channels for a chip.
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* The DAI indices for these are derived from below offsets.
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*/
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#define TEGRA186_ADMAIF_CIF_OFFSET 40
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/* I2S */
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#define I2S_CIF 0
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#define I2S_DAP 1
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#define I2S_DUMMY 2
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/* DMIC */
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#define DMIC_CIF 0
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#define DMIC_DAP 1
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#define DMIC_DUMMY 2
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/* DSPK */
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#define DSPK_CIF 0
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#define DSPK_DAP 1
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#define DSPK_DUMMY 2
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/* SFC */
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#define SFC_IN 0
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#define SFC_OUT 1
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/* MIXER */
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#define MIXER_IN1 0
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#define MIXER_IN2 1
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#define MIXER_IN3 2
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#define MIXER_IN4 3
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#define MIXER_IN5 4
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#define MIXER_IN6 5
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#define MIXER_IN7 6
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#define MIXER_IN8 7
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#define MIXER_IN9 8
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#define MIXER_IN10 9
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#define MIXER_OUT1 10
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#define MIXER_OUT2 11
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#define MIXER_OUT3 12
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#define MIXER_OUT4 13
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#define MIXER_OUT5 14
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/* AFC */
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#define AFC_IN 0
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#define AFC_OUT 1
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/* OPE */
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#define OPE_IN 0
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#define OPE_OUT 1
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/* MVC */
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#define MVC_IN 0
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#define MVC_OUT 1
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/* AMX */
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#define AMX_IN1 0
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#define AMX_IN2 1
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#define AMX_IN3 2
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#define AMX_IN4 3
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#define AMX_OUT 4
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/* ADX */
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#define ADX_IN 0
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#define ADX_OUT1 1
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#define ADX_OUT2 2
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#define ADX_OUT3 3
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#define ADX_OUT4 4
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/* ASRC */
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#define ASRC_IN1 0
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#define ASRC_IN2 1
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#define ASRC_IN3 2
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#define ASRC_IN4 3
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#define ASRC_IN5 4
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#define ASRC_IN6 5
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#define ASRC_IN7 6
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#define ASRC_OUT1 7
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#define ASRC_OUT2 8
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#define ASRC_OUT3 9
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#define ASRC_OUT4 10
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#define ASRC_OUT5 11
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#define ASRC_OUT6 12
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/* ARAD */
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#define ARAD 0
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/* ADSP */
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#define ADSP_FE1 0
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#define ADSP_FE2 1
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#define ADSP_FE3 2
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#define ADSP_FE4 3
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#define ADSP_FE5 4
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#define ADSP_FE6 5
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#define ADSP_FE7 6
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#define ADSP_FE8 7
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#define ADSP_FE9 8
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#define ADSP_FE10 9
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#define ADSP_FE11 10
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#define ADSP_FE12 11
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#define ADSP_FE13 12
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#define ADSP_FE14 13
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#define ADSP_FE15 14
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#define ADSP_EAVB_CODEC 15
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#define ADSP_ADMAIF1 16
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#define ADSP_ADMAIF2 17
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#define ADSP_ADMAIF3 18
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#define ADSP_ADMAIF4 19
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#define ADSP_ADMAIF5 20
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#define ADSP_ADMAIF6 21
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#define ADSP_ADMAIF7 22
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#define ADSP_ADMAIF8 23
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#define ADSP_ADMAIF9 24
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#define ADSP_ADMAIF10 25
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#define ADSP_ADMAIF11 26
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#define ADSP_ADMAIF12 27
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#define ADSP_ADMAIF13 28
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#define ADSP_ADMAIF14 29
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#define ADSP_ADMAIF15 30
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#define ADSP_ADMAIF16 31
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#define ADSP_ADMAIF17 32
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#define ADSP_ADMAIF18 33
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#define ADSP_ADMAIF19 34
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#define ADSP_ADMAIF20 35
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#define ADSP_PCM1 36
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#define ADSP_PCM2 37
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#define ADSP_PCM3 38
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#define ADSP_PCM4 39
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#define ADSP_PCM5 40
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#define ADSP_PCM6 41
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#define ADSP_PCM7 42
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#define ADSP_PCM8 43
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#define ADSP_PCM9 44
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#define ADSP_PCM10 45
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#define ADSP_PCM11 46
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#define ADSP_PCM12 47
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#define ADSP_PCM13 48
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#define ADSP_PCM14 49
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#define ADSP_PCM15 50
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#define ADSP_COMPR1 51
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#define ADSP_COMPR2 52
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#define ADSP_EAVB 53
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#endif
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