mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/tegra-public-dts.git
synced 2025-12-22 09:11:55 +03:00
c0baa074cc
Sync the DT binding headers for tegra234 which are required for SOC and platform DTS/DTSI from kernel V6.3-rc5. Bug 4078385 Change-Id: I96ee533ae752879ca8a3f06a732180c631cce228 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/tegra-public-dts/+/3168925 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
42 lines
1.2 KiB
C
42 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides constants for binding nvidia,tegra186-hsp.
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*/
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#ifndef _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
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#define _DT_BINDINGS_MAILBOX_TEGRA186_HSP_H
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/*
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* These define the type of mailbox that is to be used (doorbell, shared
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* mailbox, shared semaphore or arbitrated semaphore).
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*/
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#define TEGRA_HSP_MBOX_TYPE_DB 0x0
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#define TEGRA_HSP_MBOX_TYPE_SM 0x1
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#define TEGRA_HSP_MBOX_TYPE_SS 0x2
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#define TEGRA_HSP_MBOX_TYPE_AS 0x3
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/*
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* These define the types of shared mailbox supported based on data size.
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*/
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#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8)
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/*
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* These defines represent the bit associated with the given master ID in the
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* doorbell registers.
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*/
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#define TEGRA_HSP_DB_MASTER_CCPLEX 17
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#define TEGRA_HSP_DB_MASTER_BPMP 19
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/*
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* Shared mailboxes are unidirectional, so the direction needs to be specified
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* in the device tree.
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*/
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#define TEGRA_HSP_SM_MASK 0x00ffffff
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#define TEGRA_HSP_SM_FLAG_RX (0 << 31)
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#define TEGRA_HSP_SM_FLAG_TX (1 << 31)
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#define TEGRA_HSP_SM_RX(x) (TEGRA_HSP_SM_FLAG_RX | ((x) & TEGRA_HSP_SM_MASK))
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#define TEGRA_HSP_SM_TX(x) (TEGRA_HSP_SM_FLAG_TX | ((x) & TEGRA_HSP_SM_MASK))
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#endif
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