mirror of
git://nv-tegra.nvidia.com/device/hardware/nvidia/tegra-public-dts.git
synced 2025-12-22 09:11:55 +03:00
c0baa074cc
Sync the DT binding headers for tegra234 which are required for SOC and platform DTS/DTSI from kernel V6.3-rc5. Bug 4078385 Change-Id: I96ee533ae752879ca8a3f06a732180c631cce228 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/tegra-public-dts/+/3168925 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
38 lines
1.0 KiB
C
38 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This header provides constants for Tegra pinctrl bindings.
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*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* Author: Laxman Dewangan <ldewangan@nvidia.com>
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*/
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#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
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#define _DT_BINDINGS_PINCTRL_TEGRA_H
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/*
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* Enable/disable for diffeent dt properties. This is applicable for
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* properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
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* nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
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*/
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#define TEGRA_PIN_DISABLE 0
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#define TEGRA_PIN_ENABLE 1
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#define TEGRA_PIN_PULL_NONE 0
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#define TEGRA_PIN_PULL_DOWN 1
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#define TEGRA_PIN_PULL_UP 2
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/* Low power mode driver */
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#define TEGRA_PIN_LP_DRIVE_DIV_8 0
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#define TEGRA_PIN_LP_DRIVE_DIV_4 1
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#define TEGRA_PIN_LP_DRIVE_DIV_2 2
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#define TEGRA_PIN_LP_DRIVE_DIV_1 3
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/* Rising/Falling slew rate */
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#define TEGRA_PIN_SLEW_RATE_FASTEST 0
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#define TEGRA_PIN_SLEW_RATE_FAST 1
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#define TEGRA_PIN_SLEW_RATE_SLOW 2
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#define TEGRA_PIN_SLEW_RATE_SLOWEST 3
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#endif
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