mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-22 17:30:40 +03:00
tegra: hwpm: t234: use autogenerated regops allowlist
- Replace keyword whitelist with allowlist. - Update driver to use auto-genrated regops allowlist. - This will allow support for multiple chips. Jira THWPM-14 Change-Id: I076ee1b425dfef53650477518c846e9e4d4a9e23 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2605889 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
committed by
mobile promotions
mobile promotions
parent
a894ff75c0
commit
08cf289cbd
2
Makefile
2
Makefile
@@ -4,6 +4,8 @@
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GCOV_PROFILE := y
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ccflags-y += -I$(srctree.nvidia)/drivers/platform/tegra/hwpm/include/regops/t234
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obj-y += tegra-soc-hwpm.o
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obj-y += tegra-soc-hwpm-io.o
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obj-y += tegra-soc-hwpm-ioctl.o
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368
include/regops/t234/reg_allowlist.h
Normal file
368
include/regops/t234/reg_allowlist.h
Normal file
@@ -0,0 +1,368 @@
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/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* This file is autogenerated. Do not edit.
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*/
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#ifndef SOC_HWPM_REGOPS_ALLOWLIST_H
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#define SOC_HWPM_REGOPS_ALLOWLIST_H
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struct allowlist {
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u64 reg_offset;
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bool zero_at_init;
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};
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struct allowlist perfmon_alist[] = {
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{0x00000000, true},
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{0x00000004, true},
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{0x00000008, true},
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{0x0000000c, true},
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{0x00000010, true},
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{0x00000014, true},
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{0x00000020, true},
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{0x00000024, true},
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{0x00000028, true},
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{0x0000002c, true},
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{0x00000030, true},
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{0x00000034, true},
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{0x00000040, true},
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{0x00000044, true},
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{0x00000048, true},
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{0x0000004c, true},
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{0x00000050, true},
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{0x00000054, true},
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{0x00000058, true},
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{0x0000005c, true},
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{0x00000060, true},
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{0x00000064, true},
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{0x00000068, true},
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{0x0000006c, true},
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{0x00000070, true},
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{0x00000074, true},
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{0x00000078, true},
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{0x0000007c, true},
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{0x00000080, true},
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{0x00000084, true},
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{0x00000088, true},
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{0x0000008c, true},
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{0x00000090, true},
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{0x00000098, true},
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{0x0000009c, true},
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{0x000000a0, true},
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{0x000000a4, true},
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{0x000000a8, true},
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{0x000000ac, true},
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{0x000000b0, true},
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{0x000000b4, true},
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{0x000000b8, true},
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{0x000000bc, true},
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{0x000000c0, true},
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{0x000000c4, true},
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{0x000000c8, true},
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{0x000000cc, true},
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{0x000000d0, true},
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{0x000000d4, true},
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{0x000000d8, true},
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{0x000000dc, true},
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{0x000000e0, true},
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{0x000000e4, true},
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{0x000000e8, true},
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{0x000000ec, true},
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{0x000000f8, true},
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{0x000000fc, true},
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{0x00000100, true},
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{0x00000108, true},
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{0x00000110, true},
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{0x00000114, true},
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{0x00000118, true},
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{0x0000011c, true},
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{0x00000120, true},
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{0x00000124, true},
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{0x00000128, true},
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{0x00000130, true},
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};
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struct allowlist pma_res_cmd_slice_rtr_alist[] = {
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{0x00000000, false},
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{0x00000008, false},
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{0x0000000c, false},
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{0x00000010, false},
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{0x00000014, false},
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{0x0000003c, false},
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{0x00000044, false},
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{0x00000070, false},
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{0x0000008c, false},
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{0x00000600, false},
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{0x00000604, false},
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{0x00000608, false},
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{0x0000060c, false},
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{0x00000610, false},
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{0x00000618, false},
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{0x0000061c, false},
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{0x00000620, false},
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{0x00000624, false},
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{0x0000062c, false},
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{0x00000630, false},
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{0x00000634, false},
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{0x00000638, false},
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{0x0000063c, false},
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{0x00000640, false},
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{0x00000644, false},
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{0x00000648, false},
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{0x0000064c, false},
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{0x00000650, false},
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{0x00000654, false},
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{0x00000658, false},
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{0x0000065c, false},
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{0x00000660, false},
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{0x00000664, false},
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{0x00000668, false},
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{0x0000066c, false},
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{0x00000670, false},
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{0x00000674, false},
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{0x00000678, false},
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{0x0000067c, false},
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{0x00000680, false},
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{0x00000684, false},
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{0x00000688, false},
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{0x0000068c, false},
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{0x00000690, false},
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{0x00000694, false},
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{0x00000698, false},
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{0x0000069c, false},
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{0x000006a0, false},
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{0x000006a4, false},
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{0x000006a8, false},
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{0x000006ac, false},
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{0x000006b0, false},
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{0x000006b4, false},
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{0x000006b8, false},
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{0x000006bc, false},
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{0x000006c0, false},
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{0x000006c4, false},
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{0x000006c8, false},
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{0x000006cc, false},
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{0x000006d0, false},
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{0x000006d4, false},
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{0x000006d8, false},
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{0x000006dc, false},
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{0x000006e0, false},
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{0x000006e4, false},
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{0x000006e8, false},
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{0x000006ec, false},
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{0x000006f0, false},
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{0x000006f4, false},
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{0x000006f8, false},
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{0x000006fc, false},
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{0x00000700, false},
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{0x00000704, false},
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{0x00000708, false},
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{0x0000070c, false},
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{0x00000710, false},
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{0x00000714, false},
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{0x00000718, false},
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{0x0000071c, false},
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{0x00000720, false},
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{0x00000724, false},
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{0x00000728, false},
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{0x0000072c, false},
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{0x00000730, false},
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{0x00000734, false},
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{0x0000075c, false},
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};
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struct allowlist pma_res_pma_alist[] = {
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{0x00000628, true},
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};
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struct allowlist rtr_alist[] = {
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{0x00000000, false},
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{0x00000008, false},
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{0x0000000c, false},
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{0x00000010, false},
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{0x00000014, false},
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{0x00000018, false},
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{0x00000150, false},
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{0x00000154, false},
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};
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struct allowlist vi_thi_alist[] = {
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{0x0000e800, false},
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{0x0000e804, false},
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{0x0000e808, true},
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{0x0000e80c, true},
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{0x0000e810, true},
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{0x0000e814, true},
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{0x0000e818, true},
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};
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struct allowlist isp_thi_alist[] = {
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{0x000091c0, false},
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{0x000091c4, false},
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{0x000091c8, true},
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{0x000091cc, true},
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{0x000091d0, true},
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{0x000091d4, true},
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{0x000091d8, true},
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};
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struct allowlist vic_alist[] = {
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{0x00001088, false},
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{0x000010a8, false},
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{0x00001c00, true},
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{0x00001c04, true},
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{0x00001c08, true},
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{0x00001c0c, true},
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{0x00001c10, true},
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{0x00001c14, false},
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{0x00001c18, false},
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};
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struct allowlist ofa_alist[] = {
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{0x00001088, false},
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{0x000010a8, false},
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{0x00003308, true},
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{0x0000330c, true},
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{0x00003310, true},
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{0x00003314, true},
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{0x00003318, false},
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{0x0000331c, false},
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};
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struct allowlist pva0_pm_alist[] = {
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{0x00008000, false},
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{0x00008004, false},
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{0x00008008, false},
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{0x0000800c, true},
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{0x00008010, true},
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{0x00008014, true},
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{0x00008018, true},
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{0x0000801c, true},
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{0x00008020, true},
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};
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struct allowlist nvdla_alist[] = {
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{0x00001088, false},
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{0x000010a8, false},
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{0x0001a000, false},
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{0x0001a004, false},
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{0x0001a008, true},
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{0x0001a00c, true},
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{0x0001a010, true},
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{0x0001a014, true},
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{0x0001a018, true},
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{0x0001a01c, true},
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{0x0001a020, true},
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{0x0001a024, true},
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{0x0001a028, true},
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{0x0001a02c, true},
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{0x0001a030, true},
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{0x0001a034, true},
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{0x0001a038, true},
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{0x0001a03c, true},
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{0x0001a040, true},
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{0x0001a044, true},
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{0x0001a048, true},
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{0x0001a04c, true},
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{0x0001a050, true},
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{0x0001a054, true},
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{0x0001a058, true},
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{0x0001a05c, true},
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{0x0001a060, true},
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{0x0001a064, true},
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{0x0001a068, true},
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{0x0001a06c, true},
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{0x0001a070, true},
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{0x0001a074, true},
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{0x0001a078, true},
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{0x0001a07c, true},
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};
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struct allowlist mgbe_alist[] = {
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};
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struct allowlist nvdec_alist[] = {
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{0x00001088, false},
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{0x000010a8, false},
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{0x00001b48, false},
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{0x00001b4c, false},
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{0x00001b50, true},
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{0x00001b54, true},
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{0x00001b58, true},
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{0x00001b5c, true},
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};
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struct allowlist nvenc_alist[] = {
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{0x00001088, false},
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{0x000010a8, false},
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{0x00002134, true},
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{0x00002100, false},
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{0x00002120, false},
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{0x00002124, false},
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{0x00002128, false},
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{0x0000212c, false},
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{0x00002130, false},
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};
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struct allowlist pcie_ctl_alist[] = {
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{0x00000174, true},
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{0x00000178, false},
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};
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struct allowlist disp_alist[] = {
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};
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struct allowlist mss_channel_alist[] = {
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{0x00000814, true},
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{0x0000082c, true},
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};
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struct allowlist mss_nvlink_alist[] = {
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{0x00000a30, true},
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};
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struct allowlist mc0to7_res_mss_iso_niso_hub_alist[] = {
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{0x00000818, true},
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{0x0000081c, true},
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};
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struct allowlist mc8_res_mss_iso_niso_hub_alist[] = {
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{0x00000828, true},
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};
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struct allowlist mcb_mss_mcf_alist[] = {
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{0x00000800, true},
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{0x00000820, true},
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{0x0000080c, true},
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{0x00000824, true},
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};
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struct allowlist mc0to1_mss_mcf_alist[] = {
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{0x00000808, true},
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{0x00000804, true},
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{0x00000810, true},
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};
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struct allowlist mc2to7_mss_mcf_alist[] = {
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{0x00000810, true},
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};
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#endif /* SOC_HWPM_REGOPS_ALLOWLIST_H */
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File diff suppressed because it is too large
Load Diff
@@ -22,10 +22,7 @@
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#include "tegra-soc-hwpm.h"
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struct whitelist {
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u64 reg;
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bool zero_in_init;
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};
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struct allowlist;
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struct hwpm_resource_aperture {
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/*
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@@ -46,9 +43,9 @@ struct hwpm_resource_aperture {
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u64 start_pa;
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u64 end_pa;
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/* Whitelist */
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struct whitelist *wlist;
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u64 wlist_size;
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/* Allowlist */
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struct allowlist *alist;
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u64 alist_size;
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/* Fake registers for VDK which doesn't have a SOC HWPM fmodel */
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u32 *fake_registers;
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@@ -70,6 +67,10 @@ extern struct hwpm_resource_aperture mss_mcf_map[];
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extern struct hwpm_resource_aperture pma_map[];
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extern struct hwpm_resource_aperture cmd_slice_rtr_map[];
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void tegra_soc_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture);
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int tegra_soc_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm,
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void *ioctl_struct);
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struct hwpm_resource_aperture *find_hwpm_aperture(struct tegra_soc_hwpm *hwpm,
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u64 phys_addr,
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bool use_absolute_base,
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@@ -57,7 +57,7 @@ static int alloc_pma_stream_ioctl(struct tegra_soc_hwpm *hwpm,
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void *ioctl_struct);
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static int bind_ioctl(struct tegra_soc_hwpm *hwpm,
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void *ioctl_struct);
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static int query_whitelist_ioctl(struct tegra_soc_hwpm *hwpm,
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static int query_allowlist_ioctl(struct tegra_soc_hwpm *hwpm,
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void *ioctl_struct);
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static int exec_reg_ops_ioctl(struct tegra_soc_hwpm *hwpm,
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void *ioctl_struct);
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@@ -95,10 +95,10 @@ static const struct tegra_soc_hwpm_ioctl ioctls[] = {
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.struct_size = 0,
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.handler = bind_ioctl,
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},
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[TEGRA_SOC_HWPM_IOCTL_QUERY_WHITELIST] = {
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.name = "query_whitelist",
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.struct_size = sizeof(struct tegra_soc_hwpm_query_whitelist),
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.handler = query_whitelist_ioctl,
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[TEGRA_SOC_HWPM_IOCTL_QUERY_ALLOWLIST] = {
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.name = "query_allowlist",
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.struct_size = sizeof(struct tegra_soc_hwpm_query_allowlist),
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.handler = query_allowlist_ioctl,
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},
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[TEGRA_SOC_HWPM_IOCTL_EXEC_REG_OPS] = {
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.name = "exec_reg_ops",
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@@ -703,7 +703,6 @@ static int bind_ioctl(struct tegra_soc_hwpm *hwpm,
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int ret = 0;
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int res_idx = 0;
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int aprt_idx = 0;
|
||||
u32 wlist_idx = 0;
|
||||
struct hwpm_resource_aperture *aperture = NULL;
|
||||
|
||||
for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) {
|
||||
@@ -717,22 +716,12 @@ static int bind_ioctl(struct tegra_soc_hwpm *hwpm,
|
||||
aperture = &(hwpm_resources[res_idx].map[aprt_idx]);
|
||||
|
||||
/* Zero out necessary registers */
|
||||
if (aperture->wlist) {
|
||||
for (wlist_idx = 0;
|
||||
wlist_idx < aperture->wlist_size;
|
||||
wlist_idx++) {
|
||||
if (aperture->wlist[wlist_idx].zero_in_init) {
|
||||
ioctl_writel(hwpm,
|
||||
aperture,
|
||||
aperture->start_pa +
|
||||
aperture->wlist[wlist_idx].reg,
|
||||
0);
|
||||
}
|
||||
}
|
||||
if (aperture->alist) {
|
||||
tegra_soc_hwpm_zero_alist_regs(hwpm, aperture);
|
||||
} else {
|
||||
tegra_soc_hwpm_err("NULL whitelist in aperture(0x%llx - 0x%llx)",
|
||||
aperture->start_pa,
|
||||
aperture->end_pa);
|
||||
tegra_soc_hwpm_err(
|
||||
"NULL allowlist in aperture(0x%llx - 0x%llx)",
|
||||
aperture->start_pa, aperture->end_pa);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -764,142 +753,55 @@ static int bind_ioctl(struct tegra_soc_hwpm *hwpm,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int query_whitelist_ioctl(struct tegra_soc_hwpm *hwpm,
|
||||
static int query_allowlist_ioctl(struct tegra_soc_hwpm *hwpm,
|
||||
void *ioctl_struct)
|
||||
{
|
||||
int ret = 0;
|
||||
int res_idx = 0;
|
||||
int aprt_idx = 0;
|
||||
struct hwpm_resource_aperture *aperture = NULL;
|
||||
struct tegra_soc_hwpm_query_whitelist *query_whitelist =
|
||||
(struct tegra_soc_hwpm_query_whitelist *)ioctl_struct;
|
||||
struct tegra_soc_hwpm_query_allowlist *query_allowlist =
|
||||
(struct tegra_soc_hwpm_query_allowlist *)ioctl_struct;
|
||||
|
||||
if (!hwpm->bind_completed) {
|
||||
tegra_soc_hwpm_err("The QUERY_WHITELIST IOCTL can only be called"
|
||||
tegra_soc_hwpm_err("The QUERY_ALLOWLIST IOCTL can only be called"
|
||||
" after the BIND IOCTL.");
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
if (!query_whitelist->whitelist) { /* Return whitelist_size */
|
||||
if (hwpm->full_wlist_size >= 0) {
|
||||
query_whitelist->whitelist_size = hwpm->full_wlist_size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
hwpm->full_wlist_size = 0;
|
||||
for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) {
|
||||
if (!(hwpm_resources[res_idx].reserved))
|
||||
continue;
|
||||
tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx);
|
||||
|
||||
for (aprt_idx = 0;
|
||||
aprt_idx < hwpm_resources[res_idx].map_size;
|
||||
aprt_idx++) {
|
||||
aperture = &(hwpm_resources[res_idx].map[aprt_idx]);
|
||||
if (aperture->wlist) {
|
||||
hwpm->full_wlist_size += aperture->wlist_size;
|
||||
} else {
|
||||
tegra_soc_hwpm_err("NULL whitelist in aperture(0x%llx - 0x%llx)",
|
||||
aperture->start_pa,
|
||||
aperture->end_pa);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
query_whitelist->whitelist_size = hwpm->full_wlist_size;
|
||||
} else { /* Fill in whitelist array */
|
||||
unsigned long user_va =
|
||||
(unsigned long)(query_whitelist->whitelist);
|
||||
unsigned long offset = user_va & ~PAGE_MASK;
|
||||
u64 wlist_buf_size = 0;
|
||||
u64 num_pages = 0;
|
||||
long pinned_pages = 0;
|
||||
struct page **pages = NULL;
|
||||
long page_idx = 0;
|
||||
void *full_wlist = NULL;
|
||||
u64 *full_wlist_u64 = NULL;
|
||||
u32 full_wlist_idx = 0;
|
||||
u32 aprt_wlist_idx = 0;
|
||||
|
||||
if (hwpm->full_wlist_size < 0) {
|
||||
tegra_soc_hwpm_err("Invalid whitelist size");
|
||||
return -EINVAL;
|
||||
}
|
||||
wlist_buf_size = hwpm->full_wlist_size *
|
||||
sizeof(*(query_whitelist->whitelist));
|
||||
|
||||
/* Memory map user buffer into kernel address space */
|
||||
num_pages = DIV_ROUND_UP(offset + wlist_buf_size, PAGE_SIZE);
|
||||
pages = (struct page **)kzalloc(sizeof(*pages) * num_pages,
|
||||
GFP_KERNEL);
|
||||
if (!pages) {
|
||||
tegra_soc_hwpm_err("Couldn't allocate memory for pages array");
|
||||
ret = -ENOMEM;
|
||||
goto wlist_unmap;
|
||||
}
|
||||
pinned_pages = get_user_pages(user_va & PAGE_MASK,
|
||||
num_pages,
|
||||
0,
|
||||
pages,
|
||||
NULL);
|
||||
if (pinned_pages != num_pages) {
|
||||
tegra_soc_hwpm_err("Requested %llu pages / Got %ld pages",
|
||||
num_pages, pinned_pages);
|
||||
ret = -ENOMEM;
|
||||
goto wlist_unmap;
|
||||
}
|
||||
full_wlist = vmap(pages, num_pages, VM_MAP, PAGE_KERNEL);
|
||||
if (!full_wlist) {
|
||||
tegra_soc_hwpm_err("Couldn't map whitelist buffer into"
|
||||
" kernel address space");
|
||||
ret = -ENOMEM;
|
||||
goto wlist_unmap;
|
||||
}
|
||||
full_wlist_u64 = (u64 *)(full_wlist + offset);
|
||||
|
||||
/* Fill in whitelist buffer */
|
||||
for (res_idx = 0, full_wlist_idx = 0;
|
||||
res_idx < TERGA_SOC_HWPM_NUM_RESOURCES;
|
||||
res_idx++) {
|
||||
if (!(hwpm_resources[res_idx].reserved))
|
||||
continue;
|
||||
tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx);
|
||||
|
||||
for (aprt_idx = 0;
|
||||
aprt_idx < hwpm_resources[res_idx].map_size;
|
||||
aprt_idx++) {
|
||||
aperture = &(hwpm_resources[res_idx].map[aprt_idx]);
|
||||
if (aperture->wlist) {
|
||||
for (aprt_wlist_idx = 0;
|
||||
aprt_wlist_idx < aperture->wlist_size;
|
||||
aprt_wlist_idx++, full_wlist_idx++) {
|
||||
full_wlist_u64[full_wlist_idx] =
|
||||
aperture->start_pa +
|
||||
aperture->wlist[aprt_wlist_idx].reg;
|
||||
}
|
||||
} else {
|
||||
tegra_soc_hwpm_err("NULL whitelist in aperture(0x%llx - 0x%llx)",
|
||||
aperture->start_pa,
|
||||
aperture->end_pa);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
wlist_unmap:
|
||||
if (full_wlist)
|
||||
vunmap(full_wlist);
|
||||
if (pinned_pages > 0) {
|
||||
for (page_idx = 0; page_idx < pinned_pages; page_idx++) {
|
||||
set_page_dirty(pages[page_idx]);
|
||||
put_page(pages[page_idx]);
|
||||
}
|
||||
}
|
||||
if (pages)
|
||||
kfree(pages);
|
||||
if (query_allowlist->allowlist != NULL) {
|
||||
/* Concatenate allowlists and return */
|
||||
ret = tegra_soc_hwpm_update_allowlist(hwpm, ioctl_struct);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Return allowlist_size */
|
||||
if (hwpm->full_alist_size >= 0) {
|
||||
query_allowlist->allowlist_size = hwpm->full_alist_size;
|
||||
return 0;
|
||||
}
|
||||
|
||||
hwpm->full_alist_size = 0;
|
||||
for (res_idx = 0; res_idx < TERGA_SOC_HWPM_NUM_RESOURCES; res_idx++) {
|
||||
if (!(hwpm_resources[res_idx].reserved))
|
||||
continue;
|
||||
tegra_soc_hwpm_dbg("Found reserved IP(%d)", res_idx);
|
||||
|
||||
for (aprt_idx = 0;
|
||||
aprt_idx < hwpm_resources[res_idx].map_size;
|
||||
aprt_idx++) {
|
||||
aperture = &(hwpm_resources[res_idx].map[aprt_idx]);
|
||||
if (aperture->alist) {
|
||||
hwpm->full_alist_size += aperture->alist_size;
|
||||
} else {
|
||||
tegra_soc_hwpm_err(
|
||||
"NULL allowlist in aperture(0x%llx - 0x%llx)",
|
||||
aperture->start_pa, aperture->end_pa);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
query_allowlist->allowlist_size = hwpm->full_alist_size;
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -947,7 +849,7 @@ static int exec_reg_ops_ioctl(struct tegra_soc_hwpm *hwpm,
|
||||
tegra_soc_hwpm_dbg("reg op: idx(%d), phys(0x%llx), cmd(%u)",
|
||||
op_idx, reg_op->phys_addr, reg_op->cmd);
|
||||
|
||||
/* The whitelist check is done here */
|
||||
/* The allowlist check is done here */
|
||||
aperture = find_hwpm_aperture(hwpm, reg_op->phys_addr,
|
||||
true, true, &upadted_pa);
|
||||
if (!aperture) {
|
||||
@@ -1398,7 +1300,7 @@ static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp)
|
||||
|
||||
/* Initialize SW state */
|
||||
hwpm->bind_completed = false;
|
||||
hwpm->full_wlist_size = -1;
|
||||
hwpm->full_alist_size = -1;
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
@@ -86,7 +86,7 @@ struct tegra_soc_hwpm {
|
||||
|
||||
/* SW State */
|
||||
bool bind_completed;
|
||||
s32 full_wlist_size;
|
||||
s32 full_alist_size;
|
||||
|
||||
/* Debugging */
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
|
||||
Reference in New Issue
Block a user