tegra: hwpm: use kstable available APIS

- Some of the APIs are not available on stable kernel. Use kstable
specific APIs with LINUX_KERNEL macro condition.
- Temporarily comment functions that are not available on Kstable.
- Next chip headers are renamed to accommodate more than one next chip.
Update next chip includes in init.c and driver.c files.
- Rename TEGRA_SOC_HWPM_IP_INACTIVE to TEGRA_HWPM_IP_INACTIVE to follow
other macro/enum naming convention.
- Use is_resource_active() HAL instead of chip specific function.
- Create clock reset functions that will allow us to handle change in
APIs on kstable.

Jira THWPM-41

Change-Id: I55f58fa51cf9ae96ee9a9565942e68b3b2bb76ee
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2764840
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>

Makefile

@@ -11,7 +11,13 @@ ccflags-y += -I$(srctree.nvidia)/drivers/platform/tegra/hwpm
 
 # For OOT builds, set required config flags
 ifeq ($(CONFIG_TEGRA_OOT_MODULE),m)
-CONFIG_TEGRA_T234_HWPM = y
+CONFIG_TEGRA_HWPM_OOT := y
+ccflags-y += -DCONFIG_TEGRA_HWPM_OOT
+
+CONFIG_TEGRA_FUSE_UPSTREAM := y
+ccflags-y += -DCONFIG_TEGRA_FUSE_UPSTREAM
+
+CONFIG_TEGRA_T234_HWPM := y
 ccflags-y += -DCONFIG_TEGRA_T234_HWPM
 NVHWPM_OBJ = m
 else

Makefile.linux.sources

@@ -5,6 +5,7 @@
 # SPDX-License-Identifier: GPL-2.0
 
 nvhwpm-linux-objs += os/linux/aperture_utils.o
+nvhwpm-linux-objs += os/linux/clk_rst_utils.o
 nvhwpm-linux-objs += os/linux/driver.o
 nvhwpm-linux-objs += os/linux/io_utils.o
 nvhwpm-linux-objs += os/linux/ip_utils.o

common/resource.c

@@ -56,7 +56,7 @@ int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm)
 int tegra_hwpm_reserve_resource(struct tegra_soc_hwpm *hwpm, u32 resource)
 {
 	struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
-	u32 ip_idx = TEGRA_SOC_HWPM_IP_INACTIVE;
+	u32 ip_idx = TEGRA_HWPM_IP_INACTIVE;
 	int err = 0;
 
 	tegra_hwpm_fn(hwpm, " ");

hal/t234/t234_interface.c

@@ -219,7 +219,7 @@ static bool t234_hwpm_validate_hals(struct tegra_soc_hwpm *hwpm)
 bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
 	u32 ip_enum, u32 *config_ip_index)
 {
-	u32 config_ip = TEGRA_SOC_HWPM_IP_INACTIVE;
+	u32 config_ip = TEGRA_HWPM_IP_INACTIVE;
 
 	switch (ip_enum) {
 	case TEGRA_HWPM_IP_VI:
@@ -309,13 +309,13 @@ bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
 	}
 
 	*config_ip_index = config_ip;
-	return (config_ip != TEGRA_SOC_HWPM_IP_INACTIVE);
+	return (config_ip != TEGRA_HWPM_IP_INACTIVE);
 }
 
 bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
 	u32 res_enum, u32 *config_ip_index)
 {
-	u32 config_ip = TEGRA_SOC_HWPM_IP_INACTIVE;
+	u32 config_ip = TEGRA_HWPM_IP_INACTIVE;
 
 	switch (res_enum) {
 	case TEGRA_HWPM_RESOURCE_VI:
@@ -411,7 +411,7 @@ bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
 	}
 
 	*config_ip_index = config_ip;
-	return (config_ip != TEGRA_SOC_HWPM_IP_INACTIVE);
+	return (config_ip != TEGRA_HWPM_IP_INACTIVE);
 }
 
 u32 t234_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm)

hal/t234/t234_ip.c

@@ -38,7 +38,8 @@ int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
 		"Extract IP ops for resource enum %d info", resource_enum);
 
 	/* Convert tegra_soc_hwpm_resource to internal enum */
-	if (!(t234_hwpm_is_resource_active(hwpm, resource_enum, &ip_idx))) {
+	if (!(hwpm->active_chip->is_resource_active(hwpm,
+		resource_enum, &ip_idx))) {
 		tegra_hwpm_dbg(hwpm, hwpm_dbg_ip_register,
 			"SOC hwpm resource %d (base 0x%llx) is unconfigured",
 			resource_enum, base_address);

include/tegra_hwpm.h

@@ -16,7 +16,11 @@
 
 #include <tegra_hwpm_types.h>
 
-#define TEGRA_SOC_HWPM_IP_INACTIVE	~(0U)
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+#endif
+
+#define TEGRA_HWPM_IP_INACTIVE	~(0U)
 
 /* These macro values should match TEGRA_SOC_HWPM_IP_STATUS_* */
 #define TEGRA_HWPM_IP_STATUS_VALID	0U

include/tegra_hwpm_clk_rst.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TEGRA_HWPM_CLK_RST_H
+#define TEGRA_HWPM_CLK_RST_H
+
+#ifdef __KERNEL__
+#include <os/linux/clk_rst_utils.h>
+#else
+struct tegra_hwpm_os_linux;
+
+int tegra_hwpm_clk_rst_prepare_impl(struct tegra_hwpm_os_linux *hwpm_linux)
+{
+	return -EINVAL;
+}
+
+int tegra_hwpm_clk_rst_set_rate_enable_impl(
+	struct tegra_hwpm_os_linux *hwpm_linux)
+{
+	return -EINVAL;
+}
+
+int tegra_hwpm_clk_rst_disable_impl(struct tegra_hwpm_os_linux *hwpm_linux)
+{
+}
+
+void tegra_hwpm_clk_rst_release_impl(struct tegra_hwpm_os_linux *hwpm_linux)
+{
+}
+#endif
+
+#define tegra_hwpm_clk_rst_prepare(hwpm_linux)			\
+	tegra_hwpm_clk_rst_prepare_impl(hwpm_linux)
+
+#define tegra_hwpm_clk_rst_set_rate_enable(hwpm_linux)		\
+	tegra_hwpm_clk_rst_set_rate_enable_impl(hwpm_linux)
+
+#define tegra_hwpm_clk_rst_disable(hwpm_linux)			\
+	tegra_hwpm_clk_rst_disable_impl(hwpm_linux)
+
+#define tegra_hwpm_clk_rst_release(hwpm_linux)			\
+	tegra_hwpm_clk_rst_release_impl(hwpm_linux)
+
+#endif /* TEGRA_HWPM_CLK_RST_H */

include/tegra_hwpm_soc.h

@@ -14,9 +14,39 @@
 #ifndef TEGRA_HWPM_SOC_H
 #define TEGRA_HWPM_SOC_H
 
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+#define PLAT_SI				0
+#define PLAT_PRE_SI_QT			1
+#define PLAT_PRE_SI_VDK			8
+#define PLAT_PRE_SI_VSP			9
+#define PLAT_INVALID			10
+
+#define TEGRA_FUSE_PRODUCTION_MODE 0x0
+#endif
+
 #ifdef __KERNEL__
 #include <os/linux/soc_utils.h>
 #else
+u32 tegra_hwpm_get_chip_id_impl(void)
+{
+	return 0U;
+}
+
+u32 tegra_hwpm_get_major_rev_impl(void)
+{
+	return 0U;
+}
+
+u32 tegra_hwpm_chip_get_revision_impl(void)
+{
+	return 0U;
+}
+
+u32 tegra_hwpm_get_platform_impl(void)
+{
+	return 0U;
+}
+
 bool tegra_hwpm_is_platform_simulation_impl(void)
 {
 	return false;
@@ -50,6 +80,18 @@ int tegra_hwpm_fuse_readl_prod_mode_impl(struct tegra_soc_hwpm *hwpm, u32 *val)
 
 #endif
 
+#define tegra_hwpm_get_chip_id()		\
+	tegra_hwpm_get_chip_id_impl()
+
+#define tegra_hwpm_get_major_rev()		\
+	tegra_hwpm_get_major_rev_impl()
+
+#define tegra_hwpm_chip_get_revision()		\
+	tegra_hwpm_chip_get_revision_impl()
+
+#define tegra_hwpm_get_platform()		\
+	tegra_hwpm_get_platform_impl()
+
 #define tegra_hwpm_is_platform_simulation()	\
 	tegra_hwpm_is_platform_simulation_impl()
 

include/tegra_hwpm_types.h

@@ -19,6 +19,10 @@
 #include <linux/err.h>
 #include <linux/bug.h>
 #include <linux/bits.h>
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+#include <linux/bitmap.h>
+#include <linux/limits.h>
+#endif
 #endif
 
 #endif /* TEGRA_HWPM_TYPES_H */

os/linux/clk_rst_utils.c

@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <tegra_hwpm.h>
+#include <tegra_hwpm_log.h>
+#include <tegra_hwpm_soc.h>
+#include <tegra_hwpm_clk_rst.h>
+#include <os/linux/driver.h>
+
+#define LA_CLK_RATE 625000000UL
+
+int tegra_hwpm_clk_rst_prepare_impl(struct tegra_hwpm_os_linux *hwpm_linux)
+{
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	/*
+	 * Starting OOT config, clocks and resets are handled by UEFI layer
+	 * Hence, do nothing.
+	 */
+	return 0;
+#else
+	int ret = 0;
+	struct tegra_soc_hwpm *hwpm = &hwpm_linux->hwpm;
+
+	if (tegra_hwpm_is_platform_silicon()) {
+		hwpm_linux->la_clk = devm_clk_get(hwpm_linux->dev, "la");
+		if (IS_ERR(hwpm_linux->la_clk)) {
+			tegra_hwpm_err(hwpm, "Missing la clock");
+			ret = PTR_ERR(hwpm_linux->la_clk);
+			goto fail;
+		}
+
+		hwpm_linux->la_parent_clk =
+			devm_clk_get(hwpm_linux->dev, "parent");
+		if (IS_ERR(hwpm_linux->la_parent_clk)) {
+			tegra_hwpm_err(hwpm, "Missing la parent clk");
+			ret = PTR_ERR(hwpm_linux->la_parent_clk);
+			goto fail;
+		}
+
+		hwpm_linux->la_rst =
+			devm_reset_control_get(hwpm_linux->dev, "la");
+		if (IS_ERR(hwpm_linux->la_rst)) {
+			tegra_hwpm_err(hwpm, "Missing la reset");
+			ret = PTR_ERR(hwpm_linux->la_rst);
+			goto fail;
+		}
+
+		hwpm_linux->hwpm_rst =
+			devm_reset_control_get(hwpm_linux->dev, "hwpm");
+		if (IS_ERR(hwpm_linux->hwpm_rst)) {
+			tegra_hwpm_err(hwpm, "Missing hwpm reset");
+			ret = PTR_ERR(hwpm_linux->hwpm_rst);
+			goto fail;
+		}
+	}
+
+fail:
+	return ret;
+#endif
+}
+
+int tegra_hwpm_clk_rst_set_rate_enable_impl(
+	struct tegra_hwpm_os_linux *hwpm_linux)
+{
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	/*
+	 * Starting OOT config, clocks and resets are handled by UEFI layer
+	 * Hence, do nothing.
+	 */
+	return 0;
+#else
+	int ret = 0;
+	struct tegra_soc_hwpm *hwpm = &hwpm_linux->hwpm;
+
+	if (tegra_hwpm_is_platform_silicon()) {
+		ret = reset_control_assert(hwpm_linux->hwpm_rst);
+		if (ret < 0) {
+			tegra_hwpm_err(hwpm, "hwpm reset assert failed");
+			goto fail;
+		}
+		ret = reset_control_assert(hwpm_linux->la_rst);
+		if (ret < 0) {
+			tegra_hwpm_err(hwpm, "la reset assert failed");
+			goto fail;
+		}
+		/* Set required parent for la_clk */
+		if (hwpm_linux->la_clk && hwpm_linux->la_parent_clk) {
+			ret = clk_set_parent(
+				hwpm_linux->la_clk, hwpm_linux->la_parent_clk);
+			if (ret < 0) {
+				tegra_hwpm_err(hwpm,
+					"la clk set parent failed");
+				goto fail;
+			}
+		}
+		/* set la_clk rate to 625 MHZ */
+		ret = clk_set_rate(hwpm_linux->la_clk, LA_CLK_RATE);
+		if (ret < 0) {
+			tegra_hwpm_err(hwpm, "la clock set rate failed");
+			goto fail;
+		}
+		ret = clk_prepare_enable(hwpm_linux->la_clk);
+		if (ret < 0) {
+			tegra_hwpm_err(hwpm, "la clock enable failed");
+			goto fail;
+		}
+		ret = reset_control_deassert(hwpm_linux->la_rst);
+		if (ret < 0) {
+			tegra_hwpm_err(hwpm, "la reset deassert failed");
+			goto fail;
+		}
+		ret = reset_control_deassert(hwpm_linux->hwpm_rst);
+		if (ret < 0) {
+			tegra_hwpm_err(hwpm, "hwpm reset deassert failed");
+			goto fail;
+		}
+	}
+
+fail:
+	return ret;
+#endif
+}
+
+int tegra_hwpm_clk_rst_disable_impl(struct tegra_hwpm_os_linux *hwpm_linux)
+{
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	/*
+	 * Starting OOT config, clocks and resets are handled by UEFI layer
+	 * Hence, do nothing.
+	 */
+	return 0;
+#else
+	int ret = 0;
+	struct tegra_soc_hwpm *hwpm = &hwpm_linux->hwpm;
+
+	if (tegra_hwpm_is_platform_silicon()) {
+		ret = reset_control_assert(hwpm_linux->hwpm_rst);
+		if (ret < 0) {
+			tegra_hwpm_err(hwpm, "hwpm reset assert failed");
+			goto fail;
+		}
+		ret = reset_control_assert(hwpm_linux->la_rst);
+		if (ret < 0) {
+			tegra_hwpm_err(hwpm, "la reset assert failed");
+			goto fail;
+		}
+		clk_disable_unprepare(hwpm_linux->la_clk);
+	}
+fail:
+	return ret;
+#endif
+}
+
+void tegra_hwpm_clk_rst_release_impl(struct tegra_hwpm_os_linux *hwpm_linux)
+{
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	/*
+	 * Starting OOT config, clocks and resets are handled by UEFI layer
+	 * Hence, do nothing.
+	 */
+#else
+	if (tegra_hwpm_is_platform_silicon()) {
+		if (hwpm_linux->la_clk) {
+			devm_clk_put(hwpm_linux->dev, hwpm_linux->la_clk);
+		}
+		if (hwpm_linux->la_parent_clk) {
+			devm_clk_put(hwpm_linux->dev,
+				hwpm_linux->la_parent_clk);
+		}
+		if (hwpm_linux->la_rst) {
+			reset_control_assert(hwpm_linux->la_rst);
+		}
+		if (hwpm_linux->hwpm_rst) {
+			reset_control_assert(hwpm_linux->hwpm_rst);
+		}
+	}
+#endif
+}

os/linux/clk_rst_utils.h

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TEGRA_HWPM_OS_LINUX_CLK_RST_UTILS_H
+#define TEGRA_HWPM_OS_LINUX_CLK_RST_UTILS_H
+
+struct tegra_hwpm_os_linux;
+
+int tegra_hwpm_clk_rst_prepare_impl(struct tegra_hwpm_os_linux *hwpm_linux);
+int tegra_hwpm_clk_rst_set_rate_enable_impl(
+	struct tegra_hwpm_os_linux *hwpm_linux);
+int tegra_hwpm_clk_rst_disable_impl(struct tegra_hwpm_os_linux *hwpm_linux);
+void tegra_hwpm_clk_rst_release_impl(struct tegra_hwpm_os_linux *hwpm_linux);
+
+#endif /* TEGRA_HWPM_OS_LINUX_CLK_RST_UTILS_H */

os/linux/debugfs.c

@@ -11,7 +11,6 @@
  * more details.
  */
 
-#include <stddef.h>
 #include <linux/debugfs.h>
 
 #include <tegra_hwpm_log.h>

os/linux/driver.c

@@ -16,11 +16,8 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/slab.h>
-#include <linux/reset.h>
-#include <linux/clk.h>
 #include <linux/dma-buf.h>
 #include <linux/debugfs.h>
-#include <soc/tegra/fuse.h>
 
 #include <tegra_hwpm.h>
 #include <tegra_hwpm_ip.h>
@@ -28,6 +25,7 @@
 #include <tegra_hwpm_soc.h>
 #include <tegra_hwpm_kmem.h>
 #include <tegra_hwpm_common.h>
+#include <tegra_hwpm_clk_rst.h>
 #include <os/linux/debugfs.h>
 #include <os/linux/driver.h>
 
@@ -68,10 +66,10 @@ static bool tegra_hwpm_read_support_soc_tools_prop(struct platform_device *pdev)
 
 static int tegra_hwpm_init_chip_info(struct tegra_hwpm_os_linux *hwpm_linux)
 {
-	hwpm_linux->device_info.chip = tegra_get_chip_id();
+	hwpm_linux->device_info.chip = tegra_hwpm_get_chip_id();
-	hwpm_linux->device_info.chip_revision = tegra_get_major_rev();
+	hwpm_linux->device_info.chip_revision = tegra_hwpm_get_major_rev();
-	hwpm_linux->device_info.revision = tegra_chip_get_revision();
+	hwpm_linux->device_info.revision = tegra_hwpm_chip_get_revision();
-	hwpm_linux->device_info.platform = tegra_get_platform();
+	hwpm_linux->device_info.platform = tegra_hwpm_get_platform();
 
 	return 0;
 }
@@ -146,37 +144,9 @@ static int tegra_hwpm_probe(struct platform_device *pdev)
 
 	(void) dma_set_mask_and_coherent(hwpm_linux->dev, DMA_BIT_MASK(39));
 
-	if (tegra_hwpm_is_platform_silicon()) {
+	ret = tegra_hwpm_clk_rst_prepare(hwpm_linux);
-		hwpm_linux->la_clk = devm_clk_get(hwpm_linux->dev, "la");
+	if (ret != 0) {
-		if (IS_ERR(hwpm_linux->la_clk)) {
+		goto clock_reset_fail;
-			tegra_hwpm_err(hwpm, "Missing la clock");
-			ret = PTR_ERR(hwpm_linux->la_clk);
-			goto clock_reset_fail;
-		}
-
-		hwpm_linux->la_parent_clk =
-			devm_clk_get(hwpm_linux->dev, "parent");
-		if (IS_ERR(hwpm_linux->la_parent_clk)) {
-			tegra_hwpm_err(hwpm, "Missing la parent clk");
-			ret = PTR_ERR(hwpm_linux->la_parent_clk);
-			goto clock_reset_fail;
-		}
-
-		hwpm_linux->la_rst =
-			devm_reset_control_get(hwpm_linux->dev, "la");
-		if (IS_ERR(hwpm_linux->la_rst)) {
-			tegra_hwpm_err(hwpm, "Missing la reset");
-			ret = PTR_ERR(hwpm_linux->la_rst);
-			goto clock_reset_fail;
-		}
-
-		hwpm_linux->hwpm_rst =
-			devm_reset_control_get(hwpm_linux->dev, "hwpm");
-		if (IS_ERR(hwpm_linux->hwpm_rst)) {
-			tegra_hwpm_err(hwpm, "Missing hwpm reset");
-			ret = PTR_ERR(hwpm_linux->hwpm_rst);
-			goto clock_reset_fail;
-		}
 	}
 
 	tegra_hwpm_debugfs_init(hwpm_linux);
@@ -198,10 +168,11 @@ static int tegra_hwpm_probe(struct platform_device *pdev)
 	 * Currently VDK doesn't have a fmodel for SOC HWPM. Therefore, we
 	 * enable fake registers on VDK for minimal testing.
 	 */
-	if (tegra_hwpm_is_platform_simulation())
+	if (tegra_hwpm_is_platform_simulation()) {
 		hwpm->fake_registers_enabled = true;
-	else
+	} else {
 		hwpm->fake_registers_enabled = false;
+	}
 
 	platform_set_drvdata(pdev, hwpm);
 	tegra_soc_hwpm_pdev = pdev;
@@ -211,17 +182,7 @@ static int tegra_hwpm_probe(struct platform_device *pdev)
 
 init_chip_info_fail:
 init_sw_components_fail:
-	if (tegra_hwpm_is_platform_silicon()) {
+	tegra_hwpm_clk_rst_release(hwpm_linux);
-		if (hwpm_linux->la_clk)
-			devm_clk_put(hwpm_linux->dev, hwpm_linux->la_clk);
-		if (hwpm_linux->la_parent_clk)
-			devm_clk_put(hwpm_linux->dev,
-				hwpm_linux->la_parent_clk);
-		if (hwpm_linux->la_rst)
-			reset_control_assert(hwpm_linux->la_rst);
-		if (hwpm_linux->hwpm_rst)
-			reset_control_assert(hwpm_linux->hwpm_rst);
-	}
 clock_reset_fail:
 	device_destroy(&hwpm_linux->class, hwpm_linux->dev_t);
 device_create:
@@ -260,16 +221,7 @@ static int tegra_hwpm_remove(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	if (tegra_hwpm_is_platform_silicon()) {
+	tegra_hwpm_clk_rst_release(hwpm_linux);
-		if (hwpm_linux->la_clk)
-			devm_clk_put(hwpm_linux->dev, hwpm_linux->la_clk);
-		if (hwpm_linux->la_parent_clk)
-			devm_clk_put(hwpm_linux->dev, hwpm_linux->la_parent_clk);
-		if (hwpm_linux->la_rst)
-			reset_control_assert(hwpm_linux->la_rst);
-		if (hwpm_linux->hwpm_rst)
-			reset_control_assert(hwpm_linux->hwpm_rst);
-	}
 
 	tegra_hwpm_release_ip_register_node(hwpm);
 	tegra_hwpm_release_sw_setup(hwpm);

os/linux/ioctl.c

@@ -12,8 +12,6 @@
  */
 
 #include <linux/fs.h>
-#include <linux/clk.h>
-#include <linux/reset.h>
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
 #include <linux/kernel.h>
@@ -31,13 +29,12 @@
 #include <tegra_hwpm_soc.h>
 #include <tegra_hwpm_kmem.h>
 #include <tegra_hwpm_common.h>
+#include <tegra_hwpm_clk_rst.h>
 #include <tegra_hwpm_mem_mgmt.h>
 
 #include <os/linux/driver.h>
 #include <os/linux/regops_utils.h>
 
-#define LA_CLK_RATE 625000000UL
-
 static int tegra_hwpm_get_device_info_ioctl(struct tegra_soc_hwpm *hwpm,
 	struct tegra_soc_hwpm_device_info *device_info)
 {
@@ -396,48 +393,9 @@ static int tegra_hwpm_open(struct inode *inode, struct file *filp)
 		return -EAGAIN;
 	}
 
-	if (tegra_hwpm_is_platform_silicon()) {
+	ret = tegra_hwpm_clk_rst_set_rate_enable(hwpm_linux);
-		ret = reset_control_assert(hwpm_linux->hwpm_rst);
+	if (ret != 0) {
-		if (ret < 0) {
+		goto fail;
-			tegra_hwpm_err(hwpm, "hwpm reset assert failed");
-			goto fail;
-		}
-		ret = reset_control_assert(hwpm_linux->la_rst);
-		if (ret < 0) {
-			tegra_hwpm_err(hwpm, "la reset assert failed");
-			goto fail;
-		}
-		/* Set required parent for la_clk */
-		if (hwpm_linux->la_clk && hwpm_linux->la_parent_clk) {
-			ret = clk_set_parent(
-				hwpm_linux->la_clk, hwpm_linux->la_parent_clk);
-			if (ret < 0) {
-				tegra_hwpm_err(hwpm,
-					"la clk set parent failed");
-				goto fail;
-			}
-		}
-		/* set la_clk rate to 625 MHZ */
-		ret = clk_set_rate(hwpm_linux->la_clk, LA_CLK_RATE);
-		if (ret < 0) {
-			tegra_hwpm_err(hwpm, "la clock set rate failed");
-			goto fail;
-		}
-		ret = clk_prepare_enable(hwpm_linux->la_clk);
-		if (ret < 0) {
-			tegra_hwpm_err(hwpm, "la clock enable failed");
-			goto fail;
-		}
-		ret = reset_control_deassert(hwpm_linux->la_rst);
-		if (ret < 0) {
-			tegra_hwpm_err(hwpm, "la reset deassert failed");
-			goto fail;
-		}
-		ret = reset_control_deassert(hwpm_linux->hwpm_rst);
-		if (ret < 0) {
-			tegra_hwpm_err(hwpm, "hwpm reset deassert failed");
-			goto fail;
-		}
 	}
 
 	ret = tegra_hwpm_setup_hw(hwpm);
@@ -499,11 +457,6 @@ static int tegra_hwpm_release(struct inode *inode, struct file *filp)
 
 	tegra_hwpm_fn(hwpm, " ");
 
-	/* De-init driver on last close call only */
-	if (!atomic_dec_and_test(&hwpm_linux->usage_count.var)) {
-		return 0;
-	}
-
 	if (hwpm->device_opened == false) {
 		/* Device was not opened, do nothing */
 		return 0;
@@ -541,20 +494,16 @@ static int tegra_hwpm_release(struct inode *inode, struct file *filp)
 		goto fail;
 	}
 
-	if (tegra_hwpm_is_platform_silicon()) {
+	ret = tegra_hwpm_clk_rst_disable(hwpm_linux);
-		ret = reset_control_assert(hwpm_linux->hwpm_rst);
+	if (ret < 0) {
-		if (ret < 0) {
+		tegra_hwpm_err(hwpm, "Failed to release clock");
-			tegra_hwpm_err(hwpm, "hwpm reset assert failed");
+		err = ret;
-			err = ret;
+		goto fail;
-			goto fail;
+	}
-		}
+
-		ret = reset_control_assert(hwpm_linux->la_rst);
+	/* De-init driver on last close call only */
-		if (ret < 0) {
+	if (!atomic_dec_and_test(&hwpm_linux->usage_count.var)) {
-			tegra_hwpm_err(hwpm, "la reset assert failed");
+		return 0;
-			err = ret;
-			goto fail;
-		}
-		clk_disable_unprepare(hwpm_linux->la_clk);
 	}
 
 	hwpm->device_opened = false;

os/linux/ip_utils.c

@@ -12,7 +12,6 @@
  */
 
 #include <linux/slab.h>
-#include <soc/tegra/fuse.h>
 #include <uapi/linux/tegra-soc-hwpm-uapi.h>
 
 #include <tegra_hwpm_kmem.h>
@@ -196,7 +195,7 @@ int tegra_hwpm_complete_ip_register_impl(struct tegra_soc_hwpm *hwpm)
 static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm,
 	enum tegra_soc_hwpm_ip ip_enum)
 {
-	u32 ip_enum_idx = TEGRA_SOC_HWPM_IP_INACTIVE;
+	u32 ip_enum_idx = TEGRA_HWPM_IP_INACTIVE;
 
 	switch (ip_enum) {
 	case TEGRA_SOC_HWPM_IP_VI:
@@ -292,7 +291,7 @@ int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
 u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm,
 	enum tegra_soc_hwpm_resource res_enum)
 {
-	u32 res_enum_idx = TEGRA_SOC_HWPM_IP_INACTIVE;
+	u32 res_enum_idx = TEGRA_HWPM_IP_INACTIVE;
 
 	switch (res_enum) {
 	case TEGRA_SOC_HWPM_RESOURCE_VI:

os/linux/mem_mgmt_utils.c

@@ -19,7 +19,6 @@
 #include <linux/string.h>
 #include <linux/of_address.h>
 #include <linux/dma-buf.h>
-#include <soc/tegra/fuse.h>
 #include <uapi/linux/tegra-soc-hwpm-uapi.h>
 
 #include <tegra_hwpm_kmem.h>
@@ -33,6 +32,11 @@
 
 #include <os/linux/driver.h>
 
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+#include <linux/module.h>
+MODULE_IMPORT_NS(DMA_BUF);
+#endif
+
 static int tegra_hwpm_dma_map_stream_buffer(struct tegra_soc_hwpm *hwpm,
 	struct tegra_soc_hwpm_alloc_pma_stream *alloc_pma_stream)
 {
@@ -85,6 +89,9 @@ static int tegra_hwpm_dma_map_mem_bytes_buffer(struct tegra_soc_hwpm *hwpm,
 	struct tegra_soc_hwpm_alloc_pma_stream *alloc_pma_stream)
 {
 	struct tegra_hwpm_os_linux *hwpm_linux = NULL;
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	int err = 0;
+#endif
 
 	tegra_hwpm_fn(hwpm, " ");
 
@@ -96,7 +103,7 @@ static int tegra_hwpm_dma_map_mem_bytes_buffer(struct tegra_soc_hwpm *hwpm,
 
 	hwpm->mem_mgmt->mem_bytes_dma_buf =
 		dma_buf_get(tegra_hwpm_safe_cast_u64_to_s32(
-		alloc_pma_stream->mem_bytes_buf_fd));
+			alloc_pma_stream->mem_bytes_buf_fd));
 	if (IS_ERR(hwpm->mem_mgmt->mem_bytes_dma_buf)) {
 		tegra_hwpm_err(hwpm, "Unable to get mem bytes dma_buf");
 		return PTR_ERR(hwpm->mem_mgmt->mem_bytes_dma_buf);
@@ -119,6 +126,15 @@ static int tegra_hwpm_dma_map_mem_bytes_buffer(struct tegra_soc_hwpm *hwpm,
 	hwpm->mem_mgmt->mem_bytes_buf_va =
 		sg_dma_address(hwpm->mem_mgmt->mem_bytes_sgt->sgl);
 
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	err = dma_buf_vmap(hwpm->mem_mgmt->mem_bytes_dma_buf,
+		(struct dma_buf_map *)hwpm->mem_mgmt->mem_bytes_kernel);
+	if (err != 0) {
+		tegra_hwpm_err(hwpm,
+			"Unable to map mem_bytes buffer into kernel VA space");
+		return -ENOMEM;
+	}
+#else
 	hwpm->mem_mgmt->mem_bytes_kernel =
 		dma_buf_vmap(hwpm->mem_mgmt->mem_bytes_dma_buf);
 	if (!hwpm->mem_mgmt->mem_bytes_kernel) {
@@ -126,6 +142,8 @@ static int tegra_hwpm_dma_map_mem_bytes_buffer(struct tegra_soc_hwpm *hwpm,
 			"Unable to map mem_bytes buffer into kernel VA space");
 		return -ENOMEM;
 	}
+#endif
+
 	memset(hwpm->mem_mgmt->mem_bytes_kernel, 0, 32);
 
 	return 0;

os/linux/regops_utils.c

@@ -24,7 +24,7 @@ static int tegra_hwpm_exec_reg_ops(struct tegra_soc_hwpm *hwpm,
 	struct tegra_soc_hwpm_reg_op *reg_op)
 {
 	bool found = false;
-	u32 ip_idx = TEGRA_SOC_HWPM_IP_INACTIVE;
+	u32 ip_idx = TEGRA_HWPM_IP_INACTIVE;
 	u32 inst_idx = 0U, element_idx = 0U;
 	u32 a_type = 0U;
 	u32 reg_val = 0U;

os/linux/soc_utils.c

@@ -11,29 +11,109 @@
  * more details.
  */
 
-#include <soc/tegra/fuse.h>
+#include <linux/of.h>
+#include <soc/tegra/fuse-helper.h>
 
 #include <tegra_hwpm.h>
 #include <tegra_hwpm_soc.h>
 
-bool tegra_hwpm_is_platform_simulation_impl(void)
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+#if defined(CONFIG_TEGRA_NEXT1_HWPM)
+#include <os/linux/next1_soc_utils.h>
+#endif
+#endif
+
+u32 tegra_hwpm_get_chip_id_impl(void)
 {
-	return tegra_platform_is_vdk();
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	if (of_machine_is_compatible("nvidia,tegra234")) {
+		return 0x23U;
+	}
+#ifdef CONFIG_TEGRA_NEXT1_HWPM
+		return tegra_hwpm_next1_get_chip_id_impl();
+#else
+		return 0x0U;
+#endif /* CONFIG_TEGRA_NEXT1_HWPM */
+#else
+	return (u32)tegra_get_chip_id();
+#endif /* CONFIG_TEGRA_HWPM_OOT */
 }
 
-bool tegra_hwpm_is_platform_vsp_impl(void)
+u32 tegra_hwpm_get_major_rev_impl(void)
 {
-	return tegra_platform_is_vsp();
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	if (of_machine_is_compatible("nvidia,tegra234")) {
+		return 0x4U;
+	}
+#ifdef CONFIG_TEGRA_NEXT1_HWPM
+		return tegra_hwpm_next1_get_major_rev_impl();
+#else
+		return 0x0U;
+#endif /* CONFIG_TEGRA_NEXT1_HWPM */
+#else
+	return (u32)tegra_get_major_rev();
+#endif
+}
+
+u32 tegra_hwpm_chip_get_revision_impl(void)
+{
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	return 0x0U;
+#else
+	return (u32)tegra_chip_get_revision();
+#endif
+}
+
+u32 tegra_hwpm_get_platform_impl(void)
+{
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	if (of_machine_is_compatible("nvidia,tegra234")) {
+		return PLAT_SI;
+	}
+#ifdef CONFIG_TEGRA_NEXT1_HWPM
+		return tegra_hwpm_next1_get_platform_impl();
+#else
+		return PLAT_INVALID;
+#endif /* CONFIG_TEGRA_NEXT1_HWPM */
+#else
+	return (u32)tegra_get_platform();
+#endif
 }
 
 bool tegra_hwpm_is_platform_silicon_impl(void)
 {
+#if defined(CONFIG_TEGRA_HWPM_OOT)
 	return tegra_platform_is_silicon();
+#else
+	return tegra_platform_is_silicon();
+#endif
+}
+
+bool tegra_hwpm_is_platform_simulation_impl(void)
+{
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	return tegra_hwpm_get_platform() == PLAT_PRE_SI_VDK;
+#else
+	return tegra_platform_is_vdk();
+#endif
+}
+
+bool tegra_hwpm_is_platform_vsp_impl(void)
+{
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	return tegra_hwpm_get_platform() == PLAT_PRE_SI_VSP;
+#else
+	return tegra_platform_is_vsp();
+#endif
 }
 
 bool tegra_hwpm_is_hypervisor_mode_impl(void)
 {
+#if defined(CONFIG_TEGRA_HWPM_OOT)
+	return false;
+#else
 	return is_tegra_hypervisor_mode();
+#endif
 }
 
 int tegra_hwpm_fuse_readl_impl(struct tegra_soc_hwpm *hwpm,

os/linux/soc_utils.h

@@ -16,6 +16,10 @@
 
 struct tegra_soc_hwpm;
 
+u32 tegra_hwpm_get_chip_id_impl(void);
+u32 tegra_hwpm_get_major_rev_impl(void);
+u32 tegra_hwpm_chip_get_revision_impl(void);
+u32 tegra_hwpm_get_platform_impl(void);
 bool tegra_hwpm_is_platform_simulation_impl(void);
 bool tegra_hwpm_is_platform_vsp_impl(void);
 bool tegra_hwpm_is_platform_silicon_impl(void);