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tegra: hwpm: th500: Add support for PCIE

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This patch adds support for PCIE XTLQ, XTLRC,
and XALRC performance monitoring in the driver.

Bug 4287384

Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: I0c07a6eb879b1bdc8d80bb085ef2bf58afbbd94b
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2990011
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Vishal Aslot
2023-10-02 23:08:37 +00:00
committed by mobile promotions
parent 845a7137ae
commit 1b8fd6fc4b
16 changed files with 3639 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/tegra/hwpm/Makefile.th500.soc.sources
View File

@@ -72,4 +72,9 @@ nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_clink/th500_mcf_clink.o
ccflags-y += -DCONFIG_TH500_HWPM_IP_MCF_CORE
nvhwpm-th500-soc-objs += hal/th500/soc/ip/mcf_core/th500_mcf_core.o
ccflags-y += -DCONFIG_TH500_HWPM_IP_PCIE
nvhwpm-th500-soc-objs += hal/th500/soc/ip/pcie/th500_pcie_xalrc.o
nvhwpm-th500-soc-objs += hal/th500/soc/ip/pcie/th500_pcie_xtlrc.o
nvhwpm-th500-soc-objs += hal/th500/soc/ip/pcie/th500_pcie_xtlq.o
endif

80
drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h
View File

@@ -486,26 +486,66 @@
#define addr_map_rpg_pm_xtlq8_limit_r() (0x13e1cfffU)
#define addr_map_rpg_pm_xtlq9_base_r() (0x13e1d000U)
#define addr_map_rpg_pm_xtlq9_limit_r() (0x13e1dfffU)
#define addr_map_pcie_c0_ctl0_base_r() (0x14080000U)
#define addr_map_pcie_c0_ctl0_limit_r() (0x1408ffffU)
#define addr_map_pcie_c1_ctl0_base_r() (0x140a0000U)
#define addr_map_pcie_c1_ctl0_limit_r() (0x140affffU)
#define addr_map_pcie_c2_ctl0_base_r() (0x140c0000U)
#define addr_map_pcie_c2_ctl0_limit_r() (0x140cffffU)
#define addr_map_pcie_c3_ctl0_base_r() (0x140e0000U)
#define addr_map_pcie_c3_ctl0_limit_r() (0x140effffU)
#define addr_map_pcie_c4_ctl0_base_r() (0x14100000U)
#define addr_map_pcie_c4_ctl0_limit_r() (0x1410ffffU)
#define addr_map_pcie_c5_ctl0_base_r() (0x14120000U)
#define addr_map_pcie_c5_ctl0_limit_r() (0x1412ffffU)
#define addr_map_pcie_c6_ctl0_base_r() (0x14140000U)
#define addr_map_pcie_c6_ctl0_limit_r() (0x1414ffffU)
#define addr_map_pcie_c7_ctl0_base_r() (0x14160000U)
#define addr_map_pcie_c7_ctl0_limit_r() (0x1416ffffU)
#define addr_map_pcie_c8_ctl0_base_r() (0x14180000U)
#define addr_map_pcie_c8_ctl0_limit_r() (0x1418ffffU)
#define addr_map_pcie_c9_ctl0_base_r() (0x141a0000U)
#define addr_map_pcie_c9_ctl0_limit_r() (0x141affffU)
#define addr_map_pcie_c0_ctl0_xalrc_base_r() (0x14080000U)
#define addr_map_pcie_c0_ctl0_xalrc_limit_r() (0x1408ffffU)
#define addr_map_pcie_c0_ctl1_xtlq_base_r() (0x14090000U)
#define addr_map_pcie_c0_ctl1_xtlq_limit_r() (0x1409ffffU)
#define addr_map_pcie_c1_ctl0_xalrc_base_r() (0x140a0000U)
#define addr_map_pcie_c1_ctl0_xalrc_limit_r() (0x140affffU)
#define addr_map_pcie_c1_ctl1_xtlq_base_r() (0x140b0000U)
#define addr_map_pcie_c1_ctl1_xtlq_limit_r() (0x140bffffU)
#define addr_map_pcie_c2_ctl0_xalrc_base_r() (0x140c0000U)
#define addr_map_pcie_c2_ctl0_xalrc_limit_r() (0x140cffffU)
#define addr_map_pcie_c2_ctl1_xtlq_base_r() (0x140d0000U)
#define addr_map_pcie_c2_ctl1_xtlq_limit_r() (0x140dffffU)
#define addr_map_pcie_c3_ctl0_xalrc_base_r() (0x140e0000U)
#define addr_map_pcie_c3_ctl0_xalrc_limit_r() (0x140effffU)
#define addr_map_pcie_c3_ctl1_xtlq_base_r() (0x140f0000U)
#define addr_map_pcie_c3_ctl1_xtlq_limit_r() (0x140fffffU)
#define addr_map_pcie_c4_ctl0_xalrc_base_r() (0x14100000U)
#define addr_map_pcie_c4_ctl0_xalrc_limit_r() (0x1410ffffU)
#define addr_map_pcie_c4_ctl1_xtlq_base_r() (0x14110000U)
#define addr_map_pcie_c4_ctl1_xtlq_limit_r() (0x1411ffffU)
#define addr_map_pcie_c5_ctl0_xalrc_base_r() (0x14120000U)
#define addr_map_pcie_c5_ctl0_xalrc_limit_r() (0x1412ffffU)
#define addr_map_pcie_c5_ctl1_xtlq_base_r() (0x14130000U)
#define addr_map_pcie_c5_ctl1_xtlq_limit_r() (0x1413ffffU)
#define addr_map_pcie_c6_ctl0_xalrc_base_r() (0x14140000U)
#define addr_map_pcie_c6_ctl0_xalrc_limit_r() (0x1414ffffU)
#define addr_map_pcie_c6_ctl1_xtlq_base_r() (0x14150000U)
#define addr_map_pcie_c6_ctl1_xtlq_limit_r() (0x1415ffffU)
#define addr_map_pcie_c7_ctl0_xalrc_base_r() (0x14160000U)
#define addr_map_pcie_c7_ctl0_xalrc_limit_r() (0x1416ffffU)
#define addr_map_pcie_c7_ctl1_xtlq_base_r() (0x14170000U)
#define addr_map_pcie_c7_ctl1_xtlq_limit_r() (0x1417ffffU)
#define addr_map_pcie_c8_ctl0_xalrc_base_r() (0x14180000U)
#define addr_map_pcie_c8_ctl0_xalrc_limit_r() (0x1418ffffU)
#define addr_map_pcie_c8_ctl1_xtlq_base_r() (0x14190000U)
#define addr_map_pcie_c8_ctl1_xtlq_limit_r() (0x1419ffffU)
#define addr_map_pcie_c9_ctl0_xalrc_base_r() (0x141a0000U)
#define addr_map_pcie_c9_ctl0_xalrc_limit_r() (0x141affffU)
#define addr_map_pcie_c9_ctl1_xtlq_base_r() (0x141b0000U)
#define addr_map_pcie_c9_ctl1_xtlq_limit_r() (0x141bffffU)
#define addr_map_pcie_c0_ctl0_xtlrc_base_r() (0x14083000U)
#define addr_map_pcie_c0_ctl0_xtlrc_limit_r() (0x14083fffU)
#define addr_map_pcie_c1_ctl0_xtlrc_base_r() (0x140a3000U)
#define addr_map_pcie_c1_ctl0_xtlrc_limit_r() (0x140a3fffU)
#define addr_map_pcie_c2_ctl0_xtlrc_base_r() (0x140c3000U)
#define addr_map_pcie_c2_ctl0_xtlrc_limit_r() (0x140c3fffU)
#define addr_map_pcie_c3_ctl0_xtlrc_base_r() (0x140e3000U)
#define addr_map_pcie_c3_ctl0_xtlrc_limit_r() (0x140e3fffU)
#define addr_map_pcie_c4_ctl0_xtlrc_base_r() (0x14103000U)
#define addr_map_pcie_c4_ctl0_xtlrc_limit_r() (0x14103fffU)
#define addr_map_pcie_c5_ctl0_xtlrc_base_r() (0x14123000U)
#define addr_map_pcie_c5_ctl0_xtlrc_limit_r() (0x14123fffU)
#define addr_map_pcie_c6_ctl0_xtlrc_base_r() (0x14143000U)
#define addr_map_pcie_c6_ctl0_xtlrc_limit_r() (0x14143fffU)
#define addr_map_pcie_c7_ctl0_xtlrc_base_r() (0x14163000U)
#define addr_map_pcie_c7_ctl0_xtlrc_limit_r() (0x14163fffU)
#define addr_map_pcie_c8_ctl0_xtlrc_base_r() (0x14183000U)
#define addr_map_pcie_c8_ctl0_xtlrc_limit_r() (0x14183fffU)
#define addr_map_pcie_c9_ctl0_xtlrc_base_r() (0x141a3000U)
#define addr_map_pcie_c9_ctl0_xtlrc_limit_r() (0x141a3fffU)
#define addr_map_rpg_pm_ctc0_base_r() (0x13e8d000U)
#define addr_map_rpg_pm_ctc0_limit_r() (0x13e8dfffU)
#define addr_map_rpg_pm_ctc1_base_r() (0x13e8e000U)

1120
drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.c Normal file
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File diff suppressed because it is too large Load Diff

48
drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xalrc.h Normal file
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@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef TH500_HWPM_IP_PCIE_XALRC_H
#define TH500_HWPM_IP_PCIE_XALRC_H
#if defined(CONFIG_TH500_HWPM_IP_PCIE)
#define TH500_HWPM_ACTIVE_IP_PCIE_XALRC TH500_HWPM_IP_PCIE_XALRC,
/* This data should ideally be available in HW headers */
#define TH500_HWPM_IP_PCIE_XALRC_NUM_INSTANCES 10U
#define TH500_HWPM_IP_PCIE_XALRC_NUM_CORE_ELEMENT_PER_INST 1U
#define TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMON_PER_INST 1U
#define TH500_HWPM_IP_PCIE_XALRC_NUM_PERFMUX_PER_INST 1U
#define TH500_HWPM_IP_PCIE_XALRC_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip th500_hwpm_ip_pcie_xalrc;
#else
#define TH500_HWPM_ACTIVE_IP_PCIE_XALRC
#endif
#endif /* TH500_HWPM_IP_PCIE_XALRC_H */

1120
drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.c Normal file
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File diff suppressed because it is too large Load Diff

48
drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlq.h Normal file
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@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef TH500_HWPM_IP_PCIE_XTLQ_H
#define TH500_HWPM_IP_PCIE_XTLQ_H
#if defined(CONFIG_TH500_HWPM_IP_PCIE)
#define TH500_HWPM_ACTIVE_IP_PCIE_XTLQ TH500_HWPM_IP_PCIE_XTLQ,
/* This data should ideally be available in HW headers */
#define TH500_HWPM_IP_PCIE_XTLQ_NUM_INSTANCES 10U
#define TH500_HWPM_IP_PCIE_XTLQ_NUM_CORE_ELEMENT_PER_INST 1U
#define TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMON_PER_INST 1U
#define TH500_HWPM_IP_PCIE_XTLQ_NUM_PERFMUX_PER_INST 1U
#define TH500_HWPM_IP_PCIE_XTLQ_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip th500_hwpm_ip_pcie_xtlq;
#else
#define TH500_HWPM_ACTIVE_IP_PCIE_XTLQ
#endif
#endif /* TH500_HWPM_IP_PCIE_XTLQ_H */

1120
drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.c Normal file
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File diff suppressed because it is too large Load Diff

48
drivers/tegra/hwpm/hal/th500/soc/ip/pcie/th500_pcie_xtlrc.h Normal file
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@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef TH500_HWPM_IP_PCIE_XTLRC_H
#define TH500_HWPM_IP_PCIE_XTLRC_H
#if defined(CONFIG_TH500_HWPM_IP_PCIE)
#define TH500_HWPM_ACTIVE_IP_PCIE_XTLRC TH500_HWPM_IP_PCIE_XTLRC,
/* This data should ideally be available in HW headers */
#define TH500_HWPM_IP_PCIE_XTLRC_NUM_INSTANCES 10U
#define TH500_HWPM_IP_PCIE_XTLRC_NUM_CORE_ELEMENT_PER_INST 1U
#define TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMON_PER_INST 1U
#define TH500_HWPM_IP_PCIE_XTLRC_NUM_PERFMUX_PER_INST 1U
#define TH500_HWPM_IP_PCIE_XTLRC_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip th500_hwpm_ip_pcie_xtlrc;
#else
#define TH500_HWPM_ACTIVE_IP_PCIE_XTLRC
#endif
#endif /* TH500_HWPM_IP_PCIE_XTLRC_H */

10
drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c
View File

@@ -225,7 +225,15 @@ struct allowlist th500_c2c_alist[52] = {
{0x0000b0fc, false},
};
struct allowlist th500_pcie_alist[1] = {
struct allowlist th500_pcie_xtlq_alist[1] = {
{0x000039e0, true},
};
struct allowlist th500_pcie_xtlrc_alist[1] = {
{0x000004e0, true},
};
struct allowlist th500_pcie_xalrc_alist[1] = {
{0x00000470, true},
};

4
drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h
View File

@@ -30,7 +30,9 @@ extern struct allowlist th500_nvltx_alist[3];
extern struct allowlist th500_nvlctrl_alist[2];
extern struct allowlist th500_smmu_alist[1];
extern struct allowlist th500_c2c_alist[52];
extern struct allowlist th500_pcie_alist[1];
extern struct allowlist th500_pcie_xtlq_alist[1];
extern struct allowlist th500_pcie_xtlrc_alist[1];
extern struct allowlist th500_pcie_xalrc_alist[1];
extern struct allowlist th500_mss_channel_alist[2];
extern struct allowlist th500_mcf_core_alist[2];
extern struct allowlist th500_mcf_clink_alist[3];

24
drivers/tegra/hwpm/hal/th500/th500_interface.c
View File

@@ -175,8 +175,14 @@ bool th500_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
break;
#endif
#if defined(CONFIG_TH500_HWPM_IP_PCIE)
case TEGRA_HWPM_IP_PCIE:
config_ip = TH500_HWPM_IP_PCIE;
case TEGRA_HWPM_IP_PCIE_XTLQ:
config_ip = TH500_HWPM_IP_PCIE_XTLQ;
break;
case TEGRA_HWPM_IP_PCIE_XTLRC:
config_ip = TH500_HWPM_IP_PCIE_XTLRC;
break;
case TEGRA_HWPM_IP_PCIE_XALRC:
config_ip = TH500_HWPM_IP_PCIE_XALRC;
break;
#endif
#if defined(CONFIG_TH500_HWPM_IP_C2C)
@@ -257,8 +263,14 @@ bool th500_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
break;
#endif
#if defined(CONFIG_TH500_HWPM_IP_PCIE)
case TEGRA_HWPM_RESOURCE_PCIE:
config_ip = TH500_HWPM_IP_PCIE;
case TEGRA_HWPM_RESOURCE_PCIE_XTLQ:
config_ip = TH500_HWPM_IP_PCIE_XTLQ;
break;
case TEGRA_HWPM_RESOURCE_PCIE_XTLRC:
config_ip = TH500_HWPM_IP_PCIE_XTLRC;
break;
case TEGRA_HWPM_RESOURCE_PCIE_XALRC:
config_ip = TH500_HWPM_IP_PCIE_XALRC;
break;
#endif
#if defined(CONFIG_TH500_HWPM_IP_C2C)
@@ -348,7 +360,9 @@ int th500_hwpm_init_chip_info(struct tegra_soc_hwpm *hwpm)
th500_active_ip_info[TH500_HWPM_IP_NVLTX] = &th500_hwpm_ip_nvltx;
#endif
#if defined(CONFIG_TH500_HWPM_IP_PCIE)
th500_active_ip_info[TH500_HWPM_IP_PCIE] = &th500_hwpm_ip_pcie;
th500_active_ip_info[TH500_HWPM_IP_PCIE_XTLQ] = &th500_hwpm_ip_pcie_xtlq;
th500_active_ip_info[TH500_HWPM_IP_PCIE_XTLRC] = &th500_hwpm_ip_pcie_xtlrc;
th500_active_ip_info[TH500_HWPM_IP_PCIE_XALRC] = &th500_hwpm_ip_pcie_xalrc;
#endif
#if defined(CONFIG_TH500_HWPM_IP_C2C)
th500_active_ip_info[TH500_HWPM_IP_C2C] = &th500_hwpm_ip_c2c;

6
drivers/tegra/hwpm/hal/th500/th500_internal.h
View File

@@ -38,6 +38,9 @@
#include <hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.h>
#include <hal/th500/soc/ip/mcf_clink/th500_mcf_clink.h>
#include <hal/th500/soc/ip/mcf_core/th500_mcf_core.h>
#include <hal/th500/soc/ip/pcie/th500_pcie_xtlq.h>
#include <hal/th500/soc/ip/pcie/th500_pcie_xtlrc.h>
#include <hal/th500/soc/ip/pcie/th500_pcie_xalrc.h>
#define TH500_HWPM_ACTIVE_IP_MAX TH500_HWPM_IP_MAX
@@ -57,6 +60,9 @@
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_IOBHX) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_CLINK) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_CORE) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PCIE_XTLQ) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PCIE_XTLRC) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PCIE_XALRC) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MAX)
#undef DEFINE_SOC_HWPM_ACTIVE_IP

4
drivers/tegra/hwpm/hal/th500/th500_ip.c
View File

@@ -70,7 +70,9 @@ int th500_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
case TH500_HWPM_IP_NVLTX:
#endif
#if defined(CONFIG_TH500_HWPM_IP_PCIE)
case TH500_HWPM_IP_PCIE:
case TH500_HWPM_IP_PCIE_XTLQ:
case TH500_HWPM_IP_PCIE_XTLRC:
case TH500_HWPM_IP_PCIE_XALRC:
#endif
#if defined(CONFIG_TH500_HWPM_IP_C2C)
case TH500_HWPM_IP_C2C:

6
drivers/tegra/hwpm/include/tegra_hwpm.h
View File

@@ -89,6 +89,9 @@ enum tegra_hwpm_ip_enum {
TEGRA_HWPM_IP_MCF_C2C,
TEGRA_HWPM_IP_MCF_CLINK,
TEGRA_HWPM_IP_MCF_CORE,
TEGRA_HWPM_IP_PCIE_XTLQ,
TEGRA_HWPM_IP_PCIE_XTLRC,
TEGRA_HWPM_IP_PCIE_XALRC,
TERGA_HWPM_NUM_IPS
};
@@ -129,6 +132,9 @@ enum tegra_hwpm_resource_enum {
TEGRA_HWPM_RESOURCE_MCF_C2C,
TEGRA_HWPM_RESOURCE_MCF_CLINK,
TEGRA_HWPM_RESOURCE_MCF_CORE,
TEGRA_HWPM_RESOURCE_PCIE_XTLQ,
TEGRA_HWPM_RESOURCE_PCIE_XTLRC,
TEGRA_HWPM_RESOURCE_PCIE_XALRC,
TERGA_HWPM_NUM_RESOURCES
};

18
drivers/tegra/hwpm/os/linux/ip_utils.c
View File

@@ -123,6 +123,15 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm,
case TEGRA_SOC_HWPM_IP_MCF_CORE:
ip_enum_idx = TEGRA_HWPM_IP_MCF_CORE;
break;
case TEGRA_SOC_HWPM_IP_PCIE_XTLQ:
ip_enum_idx = TEGRA_HWPM_IP_PCIE_XTLQ;
break;
case TEGRA_SOC_HWPM_IP_PCIE_XTLRC:
ip_enum_idx = TEGRA_HWPM_IP_PCIE_XTLRC;
break;
case TEGRA_SOC_HWPM_IP_PCIE_XALRC:
ip_enum_idx = TEGRA_HWPM_IP_PCIE_XALRC;
break;
default:
tegra_hwpm_err(hwpm,
"Queried enum tegra_soc_hwpm_ip %d is invalid",
@@ -261,6 +270,15 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm,
case TEGRA_SOC_HWPM_RESOURCE_MCF_CORE:
res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_CORE;
break;
case TEGRA_SOC_HWPM_RESOURCE_PCIE_XTLQ:
res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE_XTLQ;
break;
case TEGRA_SOC_HWPM_RESOURCE_PCIE_XTLRC:
res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE_XTLRC;
break;
case TEGRA_SOC_HWPM_RESOURCE_PCIE_XALRC:
res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE_XALRC;
break;
default:
tegra_hwpm_err(hwpm,
"Queried enum tegra_soc_hwpm_resource %d is invalid",

6
include/uapi/linux/tegra-soc-hwpm-uapi.h
View File

@@ -56,6 +56,9 @@ enum tegra_soc_hwpm_ip {
TEGRA_SOC_HWPM_IP_MCF_C2C,
TEGRA_SOC_HWPM_IP_MCF_CLINK,
TEGRA_SOC_HWPM_IP_MCF_CORE,
TEGRA_SOC_HWPM_IP_PCIE_XTLQ,
TEGRA_SOC_HWPM_IP_PCIE_XTLRC,
TEGRA_SOC_HWPM_IP_PCIE_XALRC,
TERGA_SOC_HWPM_NUM_IPS
};
@@ -134,6 +137,9 @@ enum tegra_soc_hwpm_resource {
TEGRA_SOC_HWPM_RESOURCE_MCF_C2C,
TEGRA_SOC_HWPM_RESOURCE_MCF_CLINK,
TEGRA_SOC_HWPM_RESOURCE_MCF_CORE,
TEGRA_SOC_HWPM_RESOURCE_PCIE_XTLQ,
TEGRA_SOC_HWPM_RESOURCE_PCIE_XTLRC,
TEGRA_SOC_HWPM_RESOURCE_PCIE_XALRC,
TERGA_SOC_HWPM_NUM_RESOURCES
};