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th500: hwpm: Fix EMC Fuse Mask calculation.

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A recent change has led to EMC fuse mask calculation regression.
This is being corrected in this patch. The emc_fuse_disable mask
is set in such a way that, each bit corresponds to 4 MSS Channels.
For example, emc_fuse_disable mask=1100, corresponds to MSS_Channel0
to MSS_Channel7 being present, while MSS_Channel8 to MSS_Channel15
are floorswept. However, in HWPM Driver, the logic to represent a
floorswept IP element is indicated by '1'. Correct the logic to
indicate this.

Bug 4490868

Change-Id: Id83d9e1d983c3fbf8f58cef3a1ff45334d7eadd6
Signed-off-by: vasukis <vasukis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3122752
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
vasukis
2024-04-23 22:03:54 +00:00
committed by mobile promotions
parent 89426a7e0a
commit 1ff862c00a
1 changed files with 1 additions and 1 deletions
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2
drivers/tegra/hwpm/hal/th500/th500_ip.c
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@@ -328,7 +328,7 @@ static int th500_hwpm_validate_emc_config(struct tegra_soc_hwpm *hwpm)
* Convert floorsweep fuse value to available EMC elements.
*/
do {
if (emc_disable_fuse_val & (0x1U << emc_disable_fuse_bit_idx)) {
if (!(emc_disable_fuse_val & (0x1U << emc_disable_fuse_bit_idx))) {
emc_element_floorsweep_mask |=
(0xFU << (emc_disable_fuse_bit_idx * 4U));
}