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tegra: hwpm: t264: Add ISP IP support

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ISP is part of Camera IP. Add IP files to enable ISP IP.

Jira THWPM-90
Bug 4345706

Signed-off-by: vasukis <vasukis@nvidia.com>
Change-Id: I2458181b89234bcf50a674de7697dc961407922d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3263621
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Yifei Wan <ywan@nvidia.com>
This commit is contained in:
vasukis
2024-12-06 21:01:00 +00:00
committed by mobile promotions
parent 9785a43b05
commit 474df3d0b4
9 changed files with 381 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/tegra/hwpm/hal/t264/hw/t264_addr_map_soc_hwpm.h
View File

@@ -343,5 +343,13 @@
#define addr_map_vi_thi_limit_r() (0x81887fffffU)
#define addr_map_vi2_thi_base_r() (0x8188f00000U)
#define addr_map_vi2_thi_limit_r() (0x8188ffffffU)
#define addr_map_rpg_pm_isp0_base_r() (0x8181602000U)
#define addr_map_rpg_pm_isp0_limit_r() (0x8181602fffU)
#define addr_map_rpg_pm_isp1_base_r() (0x8181603000U)
#define addr_map_rpg_pm_isp1_limit_r() (0x8181603fffU)
#define addr_map_isp_thi_base_r() (0x8188b00000U)
#define addr_map_isp_thi_limit_r() (0x8188bfffffU)
#define addr_map_isp1_thi_base_r() (0x818ab00000U)
#define addr_map_isp1_thi_limit_r() (0x818abfffffU)
#define addr_map_pmc_misc_base_r() (0xc9c0000U)
#endif /* T264_ADDR_MAP_SOC_HWPM_H */

300
drivers/tegra/hwpm/hal/t264/ip/isp/t264_isp.c Normal file
View File

@@ -0,0 +1,300 @@
// SPDX-License-Identifier: MIT
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#include "t264_isp.h"
#include <tegra_hwpm.h>
#include <hal/t264/t264_regops_allowlist.h>
#include <hal/t264/t264_perfmon_device_index.h>
#include <hal/t264/hw/t264_addr_map_soc_hwpm.h>
static struct hwpm_ip_aperture t264_isp_inst0_perfmon_element_static_array[
T264_HWPM_IP_ISP_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
.name = "perfmon_isp0",
.device_index = T264_ISP0_PERFMON_DEVICE_NODE_INDEX,
.start_abs_pa = addr_map_rpg_pm_isp0_base_r(),
.end_abs_pa = addr_map_rpg_pm_isp0_limit_r(),
.start_pa = addr_map_rpg_pm_isp0_base_r(),
.end_pa = addr_map_rpg_pm_isp0_limit_r(),
.base_pa = addr_map_rpg_grp_vision_base_r(),
.alist = t264_perfmon_alist,
.alist_size = ARRAY_SIZE(t264_perfmon_alist),
.fake_registers = NULL,
},
};
static struct hwpm_ip_aperture t264_isp_inst1_perfmon_element_static_array[
T264_HWPM_IP_ISP_NUM_PERFMON_PER_INST] = {
{
.element_type = HWPM_ELEMENT_PERFMON,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
.name = "perfmon_isp1",
.device_index = T264_ISP1_PERFMON_DEVICE_NODE_INDEX,
.start_abs_pa = addr_map_rpg_pm_isp1_base_r(),
.end_abs_pa = addr_map_rpg_pm_isp1_limit_r(),
.start_pa = addr_map_rpg_pm_isp1_base_r(),
.end_pa = addr_map_rpg_pm_isp1_limit_r(),
.base_pa = addr_map_rpg_grp_vision_base_r(),
.alist = t264_perfmon_alist,
.alist_size = ARRAY_SIZE(t264_perfmon_alist),
.fake_registers = NULL,
},
};
static struct hwpm_ip_aperture t264_isp_inst0_perfmux_element_static_array[
T264_HWPM_IP_ISP_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_isp_thi_base_r(),
.end_abs_pa = addr_map_isp_thi_limit_r(),
.start_pa = addr_map_isp_thi_base_r(),
.end_pa = addr_map_isp_thi_limit_r(),
.base_pa = 0ULL,
.alist = t264_isp_alist,
.alist_size = ARRAY_SIZE(t264_isp_alist),
.fake_registers = NULL,
},
};
static struct hwpm_ip_aperture t264_isp_inst1_perfmux_element_static_array[
T264_HWPM_IP_ISP_NUM_PERFMUX_PER_INST] = {
{
.element_type = IP_ELEMENT_PERFMUX,
.aperture_index = 0U,
.element_index_mask = BIT(0),
.element_index = 0U,
.dt_mmio = NULL,
.name = {'\0'},
.start_abs_pa = addr_map_isp1_thi_base_r(),
.end_abs_pa = addr_map_isp1_thi_limit_r(),
.start_pa = addr_map_isp1_thi_base_r(),
.end_pa = addr_map_isp1_thi_limit_r(),
.base_pa = 0ULL,
.alist = t264_isp_alist,
.alist_size = ARRAY_SIZE(t264_isp_alist),
.fake_registers = NULL,
},
};
/* IP instance array */
static struct hwpm_ip_inst t264_isp_inst_static_array[
T264_HWPM_IP_ISP_NUM_INSTANCES] = {
{
.hw_inst_mask = BIT(0),
.num_core_elements_per_inst =
T264_HWPM_IP_ISP_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
.num_element_per_inst =
T264_HWPM_IP_ISP_NUM_PERFMUX_PER_INST,
.element_static_array =
t264_isp_inst0_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_isp_thi_base_r(),
.range_end = addr_map_isp_thi_limit_r(),
.element_stride = addr_map_isp_thi_limit_r() -
addr_map_isp_thi_base_r() + 1ULL,
.element_slots = 0U,
.element_arr = NULL,
},
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_BROADCAST
*/
{
.num_element_per_inst =
T264_HWPM_IP_ISP_NUM_BROADCAST_PER_INST,
.element_static_array = NULL,
.range_start = 0ULL,
.range_end = 0ULL,
.element_stride = 0ULL,
.element_slots = 0U,
.element_arr = NULL,
},
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_PERFMON
*/
{
.num_element_per_inst =
T264_HWPM_IP_ISP_NUM_PERFMON_PER_INST,
.element_static_array =
t264_isp_inst0_perfmon_element_static_array,
.range_start = addr_map_rpg_pm_isp0_base_r(),
.range_end = addr_map_rpg_pm_isp0_limit_r(),
.element_stride = addr_map_rpg_pm_isp0_limit_r() -
addr_map_rpg_pm_isp0_base_r() + 1ULL,
.element_slots = 0U,
.element_arr = NULL,
},
},
.ip_ops = {
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "",
},
{
.hw_inst_mask = BIT(1),
.num_core_elements_per_inst =
T264_HWPM_IP_ISP_NUM_CORE_ELEMENT_PER_INST,
.element_info = {
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
.num_element_per_inst =
T264_HWPM_IP_ISP_NUM_PERFMUX_PER_INST,
.element_static_array =
t264_isp_inst1_perfmux_element_static_array,
/* NOTE: range should be in ascending order */
.range_start = addr_map_isp1_thi_base_r(),
.range_end = addr_map_isp1_thi_limit_r(),
.element_stride = addr_map_isp1_thi_limit_r() -
addr_map_isp1_thi_base_r() + 1ULL,
.element_slots = 0U,
.element_arr = NULL,
},
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_BROADCAST
*/
{
.num_element_per_inst =
T264_HWPM_IP_ISP_NUM_BROADCAST_PER_INST,
.element_static_array = NULL,
.range_start = 0ULL,
.range_end = 0ULL,
.element_stride = 0ULL,
.element_slots = 0U,
.element_arr = NULL,
},
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_PERFMON
*/
{
.num_element_per_inst =
T264_HWPM_IP_ISP_NUM_PERFMON_PER_INST,
.element_static_array =
t264_isp_inst1_perfmon_element_static_array,
.range_start = addr_map_rpg_pm_isp1_base_r(),
.range_end = addr_map_rpg_pm_isp1_limit_r(),
.element_stride = addr_map_rpg_pm_isp1_limit_r() -
addr_map_rpg_pm_isp1_base_r() + 1ULL,
.element_slots = 0U,
.element_arr = NULL,
},
},
.ip_ops = {
.ip_dev = NULL,
.hwpm_ip_pm = NULL,
.hwpm_ip_reg_op = NULL,
.fd = TEGRA_HWPM_IP_DEBUG_FD_INVALID,
},
.element_fs_mask = 0U,
.dev_name = "",
},
};
/* IP structure */
struct hwpm_ip t264_hwpm_ip_isp = {
.num_instances = T264_HWPM_IP_ISP_NUM_INSTANCES,
.ip_inst_static_array = t264_isp_inst_static_array,
.inst_aperture_info = {
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_PERFMUX
*/
{
/* NOTE: range should be in ascending order */
.range_start = addr_map_isp_thi_base_r(),
.range_end = addr_map_isp1_thi_limit_r(),
.inst_stride = addr_map_isp_thi_limit_r() -
addr_map_isp_thi_base_r() + 1ULL,
.inst_slots = 0U,
.inst_arr = NULL,
},
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_BROADCAST
*/
{
.range_start = 0ULL,
.range_end = 0ULL,
.inst_stride = 0ULL,
.inst_slots = 0U,
.inst_arr = NULL,
},
/*
* Instance info corresponding to
* TEGRA_HWPM_APERTURE_TYPE_PERFMON
*/
{
.range_start = addr_map_rpg_pm_isp0_base_r(),
.range_end = addr_map_rpg_pm_isp1_limit_r(),
.inst_stride = addr_map_rpg_pm_isp0_limit_r() -
addr_map_rpg_pm_isp0_base_r() + 1ULL,
.inst_slots = 0U,
.inst_arr = NULL,
},
},
.dependent_fuse_mask = TEGRA_HWPM_FUSE_OPT_HWPM_DISABLE_MASK | TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK,
.override_enable = false,
.inst_fs_mask = 0U,
.resource_status = TEGRA_HWPM_RESOURCE_STATUS_INVALID,
.reserved = false,
};

48
drivers/tegra/hwpm/hal/t264/ip/isp/t264_isp.h Normal file
View File

@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef T264_HWPM_IP_ISP_H
#define T264_HWPM_IP_ISP_H
#if defined(CONFIG_T264_HWPM_IP_ISP)
#define T264_HWPM_ACTIVE_IP_ISP T264_HWPM_IP_ISP,
/* This data should ideally be available in HW headers */
#define T264_HWPM_IP_ISP_NUM_INSTANCES 2U
#define T264_HWPM_IP_ISP_NUM_CORE_ELEMENT_PER_INST 1U
#define T264_HWPM_IP_ISP_NUM_PERFMON_PER_INST 1U
#define T264_HWPM_IP_ISP_NUM_PERFMUX_PER_INST 1U
#define T264_HWPM_IP_ISP_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip t264_hwpm_ip_isp;
#else
#define T264_HWPM_ACTIVE_IP_ISP
#endif
#endif /* T264_HWPM_IP_ISP_H */

13
drivers/tegra/hwpm/hal/t264/t264_interface.c
View File

@@ -165,6 +165,11 @@ bool t264_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
config_ip = T264_HWPM_IP_VI;
#endif
break;
#if defined(CONFIG_T264_HWPM_IP_ISP)
case TEGRA_HWPM_IP_ISP:
config_ip = T264_HWPM_IP_ISP;
#endif
break;
#if defined(CONFIG_T264_HWPM_IP_SMMU)
case TEGRA_HWPM_IP_SMMU:
config_ip = T264_HWPM_IP_SMMU;
@@ -236,6 +241,11 @@ bool t264_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
config_ip = T264_HWPM_IP_VI;
#endif
break;
#if defined(CONFIG_T264_HWPM_IP_ISP)
case TEGRA_HWPM_IP_ISP:
config_ip = T264_HWPM_IP_ISP;
#endif
break;
#if defined(CONFIG_T264_HWPM_IP_SMMU)
case TEGRA_HWPM_RESOURCE_SMMU:
config_ip = T264_HWPM_IP_SMMU;
@@ -338,6 +348,9 @@ int t264_hwpm_init_chip_info(struct tegra_soc_hwpm *hwpm)
#endif
#if defined(CONFIG_T264_HWPM_IP_VI)
t264_active_ip_info[T264_HWPM_IP_VI] = &t264_hwpm_ip_vi;
#endif
#if defined(CONFIG_T264_HWPM_IP_ISP)
t264_active_ip_info[T264_HWPM_IP_ISP] = &t264_hwpm_ip_isp;
#endif
if (!tegra_hwpm_validate_primary_hals(hwpm)) {
return -EINVAL;

2
drivers/tegra/hwpm/hal/t264/t264_internal.h
View File

@@ -35,6 +35,7 @@
#include <hal/t264/ip/ucf_csw/t264_ucf_csw.h>
#include <hal/t264/ip/cpu/t264_cpu.h>
#include <hal/t264/ip/vi/t264_vi.h>
#include <hal/t264/ip/isp/t264_isp.h>
#include <hal/t264/ip/pma/t264_pma.h>
#include <hal/t264/ip/rtr/t264_rtr.h>
@@ -57,6 +58,7 @@
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_UCF_CSW) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_CPU) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_VI) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_ISP) \
DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_MAX)
enum t264_hwpm_active_ips {

3
drivers/tegra/hwpm/hal/t264/t264_ip.c
View File

@@ -83,6 +83,9 @@ int t264_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
#endif
#if defined(CONFIG_T264_HWPM_IP_VI)
case T264_HWPM_IP_VI:
#endif
#if defined(CONFIG_T264_HWPM_IP_ISP)
case T264_HWPM_IP_ISP:
#endif
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
base_address, ip_idx, available);

2
drivers/tegra/hwpm/hal/t264/t264_perfmon_device_index.h
View File

@@ -88,6 +88,8 @@ enum t264_hwpm_perfmon_device_index {
T264_UCF_TCU2_PERFMON_DEVICE_NODE_INDEX,
T264_VI0_PERFMON_DEVICE_NODE_INDEX,
T264_VI1_PERFMON_DEVICE_NODE_INDEX,
T264_ISP0_PERFMON_DEVICE_NODE_INDEX,
T264_ISP1_PERFMON_DEVICE_NODE_INDEX,
T264_VICA0_PERFMON_DEVICE_NODE_INDEX,
T264_PVAC0_PERFMON_DEVICE_NODE_INDEX,
T264_PVAV0_PERFMON_DEVICE_NODE_INDEX,

4
drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.c
View File

@@ -227,3 +227,7 @@ struct allowlist t264_cpucore_alist[4] = {
struct allowlist t264_vi_alist[1] = {
{0x0000c004, true},
};
struct allowlist t264_isp_alist[1] = {
{0x0000c004, true},
};

1
drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.h
View File

@@ -44,5 +44,6 @@ extern struct allowlist t264_ucf_psn_psw_alist[2];
extern struct allowlist t264_ucf_csw_alist[2];
extern struct allowlist t264_cpucore_alist[4];
extern struct allowlist t264_vi_alist[1];
extern struct allowlist t264_isp_alist[1];
#endif /* T264_HWPM_REGOPS_ALLOWLIST_H */