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tegra: hwpm: th500: Add support for CL2

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This patch adds support for CL2 (LTS) performance
monitoring in the driver.

Bug 4287384

Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Change-Id: Ieed663f0149bc52576fcf6d71de0e627b11fdc84
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2988343
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Vishal Aslot
2023-09-29 15:09:16 +00:00
committed by mobile promotions
parent 095e1bafd8
commit 6e75fd7b50
11 changed files with 1161 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/tegra/hwpm/Makefile.th500.soc.sources
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@@ -46,4 +46,7 @@ nvhwpm-th500-objs += hal/th500/soc/ip/c2c/th500_c2c.o
ccflags-y += -DCONFIG_TH500_HWPM_IP_SMMU ccflags-y += -DCONFIG_TH500_HWPM_IP_SMMU
nvhwpm-th500-soc-objs += hal/th500/soc/ip/smmu/th500_smmu.o nvhwpm-th500-soc-objs += hal/th500/soc/ip/smmu/th500_smmu.o
ccflags-y += -DCONFIG_TH500_HWPM_IP_CL2
nvhwpm-th500-soc-objs += hal/th500/soc/ip/cl2/th500_cl2.o
endif endif

64
drivers/tegra/hwpm/hal/th500/soc/hw/th500_addr_map_soc_hwpm.h
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@@ -188,38 +188,38 @@
#define addr_map_mc30_limit_r() (0x0441ffffU) #define addr_map_mc30_limit_r() (0x0441ffffU)
#define addr_map_mc31_base_r() (0x04420000U) #define addr_map_mc31_base_r() (0x04420000U)
#define addr_map_mc31_limit_r() (0x0443ffffU) #define addr_map_mc31_limit_r() (0x0443ffffU)
#define addr_map_rpg_pm_lts0_base_r() (0x13e3f000U) #define addr_map_rpg_pm_ltc0s0_base_r() (0x13e3f000U)
#define addr_map_rpg_pm_lts0_limit_r() (0x13e3ffffU) #define addr_map_rpg_pm_ltc0s0_limit_r() (0x13e3ffffU)
#define addr_map_rpg_pm_lts1_base_r() (0x13e40000U) #define addr_map_rpg_pm_ltc0s1_base_r() (0x13e40000U)
#define addr_map_rpg_pm_lts1_limit_r() (0x13e40fffU) #define addr_map_rpg_pm_ltc0s1_limit_r() (0x13e40fffU)
#define addr_map_rpg_pm_lts2_base_r() (0x13e41000U) #define addr_map_rpg_pm_ltc1s0_base_r() (0x13e41000U)
#define addr_map_rpg_pm_lts2_limit_r() (0x13e41fffU) #define addr_map_rpg_pm_ltc1s0_limit_r() (0x13e41fffU)
#define addr_map_rpg_pm_lts3_base_r() (0x13e42000U) #define addr_map_rpg_pm_ltc1s1_base_r() (0x13e42000U)
#define addr_map_rpg_pm_lts3_limit_r() (0x13e42fffU) #define addr_map_rpg_pm_ltc1s1_limit_r() (0x13e42fffU)
#define addr_map_rpg_pm_lts4_base_r() (0x13e43000U) #define addr_map_rpg_pm_ltc2s0_base_r() (0x13e43000U)
#define addr_map_rpg_pm_lts4_limit_r() (0x13e43fffU) #define addr_map_rpg_pm_ltc2s0_limit_r() (0x13e43fffU)
#define addr_map_rpg_pm_lts5_base_r() (0x13e44000U) #define addr_map_rpg_pm_ltc2s1_base_r() (0x13e44000U)
#define addr_map_rpg_pm_lts5_limit_r() (0x13e44fffU) #define addr_map_rpg_pm_ltc2s1_limit_r() (0x13e44fffU)
#define addr_map_rpg_pm_lts6_base_r() (0x13e45000U) #define addr_map_rpg_pm_ltc3s0_base_r() (0x13e45000U)
#define addr_map_rpg_pm_lts6_limit_r() (0x13e45fffU) #define addr_map_rpg_pm_ltc3s0_limit_r() (0x13e45fffU)
#define addr_map_rpg_pm_lts7_base_r() (0x13e46000U) #define addr_map_rpg_pm_ltc3s1_base_r() (0x13e46000U)
#define addr_map_rpg_pm_lts7_limit_r() (0x13e46fffU) #define addr_map_rpg_pm_ltc3s1_limit_r() (0x13e46fffU)
#define addr_map_rpg_pm_lts8_base_r() (0x13e47000U) #define addr_map_rpg_pm_ltc4s0_base_r() (0x13e47000U)
#define addr_map_rpg_pm_lts8_limit_r() (0x13e47fffU) #define addr_map_rpg_pm_ltc4s0_limit_r() (0x13e47fffU)
#define addr_map_rpg_pm_lts9_base_r() (0x13e48000U) #define addr_map_rpg_pm_ltc4s1_base_r() (0x13e48000U)
#define addr_map_rpg_pm_lts9_limit_r() (0x13e48fffU) #define addr_map_rpg_pm_ltc4s1_limit_r() (0x13e48fffU)
#define addr_map_rpg_pm_lts10_base_r() (0x13e49000U) #define addr_map_rpg_pm_ltc5s0_base_r() (0x13e49000U)
#define addr_map_rpg_pm_lts10_limit_r() (0x13e49fffU) #define addr_map_rpg_pm_ltc5s0_limit_r() (0x13e49fffU)
#define addr_map_rpg_pm_lts11_base_r() (0x13e4a000U) #define addr_map_rpg_pm_ltc5s1_base_r() (0x13e4a000U)
#define addr_map_rpg_pm_lts11_limit_r() (0x13e4afffU) #define addr_map_rpg_pm_ltc5s1_limit_r() (0x13e4afffU)
#define addr_map_rpg_pm_lts12_base_r() (0x13e4b000U) #define addr_map_rpg_pm_ltc6s0_base_r() (0x13e4b000U)
#define addr_map_rpg_pm_lts12_limit_r() (0x13e4bfffU) #define addr_map_rpg_pm_ltc6s0_limit_r() (0x13e4bfffU)
#define addr_map_rpg_pm_lts13_base_r() (0x13e4c000U) #define addr_map_rpg_pm_ltc6s1_base_r() (0x13e4c000U)
#define addr_map_rpg_pm_lts13_limit_r() (0x13e4cfffU) #define addr_map_rpg_pm_ltc6s1_limit_r() (0x13e4cfffU)
#define addr_map_rpg_pm_lts14_base_r() (0x13e4d000U) #define addr_map_rpg_pm_ltc7s0_base_r() (0x13e4d000U)
#define addr_map_rpg_pm_lts14_limit_r() (0x13e4dfffU) #define addr_map_rpg_pm_ltc7s0_limit_r() (0x13e4dfffU)
#define addr_map_rpg_pm_lts15_base_r() (0x13e4e000U) #define addr_map_rpg_pm_ltc7s1_base_r() (0x13e4e000U)
#define addr_map_rpg_pm_lts15_limit_r() (0x13e4efffU) #define addr_map_rpg_pm_ltc7s1_limit_r() (0x13e4efffU)
#define addr_map_ltc0_base_r() (0x04e10000U) #define addr_map_ltc0_base_r() (0x04e10000U)
#define addr_map_ltc0_limit_r() (0x04e1ffffU) #define addr_map_ltc0_limit_r() (0x04e1ffffU)
#define addr_map_ltc1_base_r() (0x04e20000U) #define addr_map_ltc1_base_r() (0x04e20000U)

1042
drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.c Normal file
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File diff suppressed because it is too large Load Diff

48
drivers/tegra/hwpm/hal/th500/soc/ip/cl2/th500_cl2.h Normal file
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@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: MIT */
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* This is a generated file. Do not edit.
*
* Steps to regenerate:
* python3 ip_files_generator.py <soc_chip> <IP_name> [<dir_name>]
*/
#ifndef TH500_HWPM_IP_CL2_H
#define TH500_HWPM_IP_CL2_H
#if defined(CONFIG_TH500_HWPM_IP_CL2)
#define TH500_HWPM_ACTIVE_IP_CL2 TH500_HWPM_IP_CL2,
/* This data should ideally be available in HW headers */
#define TH500_HWPM_IP_CL2_NUM_INSTANCES 8U
#define TH500_HWPM_IP_CL2_NUM_CORE_ELEMENT_PER_INST 1U
#define TH500_HWPM_IP_CL2_NUM_PERFMON_PER_INST 2U
#define TH500_HWPM_IP_CL2_NUM_PERFMUX_PER_INST 1U
#define TH500_HWPM_IP_CL2_NUM_BROADCAST_PER_INST 0U
extern struct hwpm_ip th500_hwpm_ip_cl2;
#else
#define TH500_HWPM_ACTIVE_IP_CL2
#endif
#endif /* TH500_HWPM_IP_CL2_H */

32
drivers/tegra/hwpm/hal/th500/soc/th500_soc_perfmon_device_index.h
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@@ -87,22 +87,22 @@ enum th500_hwpm_soc_perfmon_device_index {
TH500_MSS_CHANNEL_PARTH1_PERFMON_DEVICE_NODE_INDEX, TH500_MSS_CHANNEL_PARTH1_PERFMON_DEVICE_NODE_INDEX,
TH500_MSS_CHANNEL_PARTH2_PERFMON_DEVICE_NODE_INDEX, TH500_MSS_CHANNEL_PARTH2_PERFMON_DEVICE_NODE_INDEX,
TH500_MSS_CHANNEL_PARTH3_PERFMON_DEVICE_NODE_INDEX, TH500_MSS_CHANNEL_PARTH3_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS0_PERFMON_DEVICE_NODE_INDEX, TH500_LTC0S0_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS1_PERFMON_DEVICE_NODE_INDEX, TH500_LTC0S1_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS2_PERFMON_DEVICE_NODE_INDEX, TH500_LTC1S0_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS3_PERFMON_DEVICE_NODE_INDEX, TH500_LTC1S1_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS4_PERFMON_DEVICE_NODE_INDEX, TH500_LTC2S0_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS5_PERFMON_DEVICE_NODE_INDEX, TH500_LTC2S1_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS6_PERFMON_DEVICE_NODE_INDEX, TH500_LTC3S0_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS7_PERFMON_DEVICE_NODE_INDEX, TH500_LTC3S1_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS8_PERFMON_DEVICE_NODE_INDEX, TH500_LTC4S0_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS9_PERFMON_DEVICE_NODE_INDEX, TH500_LTC4S1_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS10_PERFMON_DEVICE_NODE_INDEX, TH500_LTC5S0_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS11_PERFMON_DEVICE_NODE_INDEX, TH500_LTC5S1_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS12_PERFMON_DEVICE_NODE_INDEX, TH500_LTC6S0_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS13_PERFMON_DEVICE_NODE_INDEX, TH500_LTC6S1_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS14_PERFMON_DEVICE_NODE_INDEX, TH500_LTC7S0_PERFMON_DEVICE_NODE_INDEX,
TH500_LTS15_PERFMON_DEVICE_NODE_INDEX, TH500_LTC7S1_PERFMON_DEVICE_NODE_INDEX,
TH500_MCFCORE0_PERFMON_DEVICE_NODE_INDEX, TH500_MCFCORE0_PERFMON_DEVICE_NODE_INDEX,
TH500_MCFCORE1_PERFMON_DEVICE_NODE_INDEX, TH500_MCFCORE1_PERFMON_DEVICE_NODE_INDEX,
TH500_MCFCORE2_PERFMON_DEVICE_NODE_INDEX, TH500_MCFCORE2_PERFMON_DEVICE_NODE_INDEX,

7
drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.c
View File

@@ -244,3 +244,10 @@ struct allowlist th500_soc_hub_alist[3] = {
{0x00006f38, false}, {0x00006f38, false},
{0x00006f3c, false}, {0x00006f3c, false},
}; };
struct allowlist th500_cl2_alist[4] = {
{0x00000550, false},
{0x00000578, false},
{0x00000750, false},
{0x00000778, false},
};

1
drivers/tegra/hwpm/hal/th500/soc/th500_soc_regops_allowlist.h
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@@ -35,5 +35,6 @@ extern struct allowlist th500_mcf_clink_alist[3];
extern struct allowlist th500_mcf_c2c_alist[2]; extern struct allowlist th500_mcf_c2c_alist[2];
extern struct allowlist th500_mcf_soc_alist[2]; extern struct allowlist th500_mcf_soc_alist[2];
extern struct allowlist th500_soc_hub_alist[3]; extern struct allowlist th500_soc_hub_alist[3];
extern struct allowlist th500_cl2_alist[4];
#endif /* TH500_HWPM_REGOPS_ALLOWLIST_H */ #endif /* TH500_HWPM_REGOPS_ALLOWLIST_H */

2
drivers/tegra/hwpm/hal/th500/th500_internal.h
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@@ -28,6 +28,7 @@
#include <hal/th500/soc/ip/pma/th500_pma.h> #include <hal/th500/soc/ip/pma/th500_pma.h>
#include <hal/th500/soc/ip/c2c/th500_c2c.h> #include <hal/th500/soc/ip/c2c/th500_c2c.h>
#include <hal/th500/soc/ip/smmu/th500_smmu.h> #include <hal/th500/soc/ip/smmu/th500_smmu.h>
#include <hal/th500/soc/ip/cl2/th500_cl2.h>
#define TH500_HWPM_ACTIVE_IP_MAX TH500_HWPM_IP_MAX #define TH500_HWPM_ACTIVE_IP_MAX TH500_HWPM_IP_MAX
@@ -37,6 +38,7 @@
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MSS_CHANNEL) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MSS_CHANNEL) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_C2C) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_C2C) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_SMMU) \ DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_SMMU) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_CL2) \
DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MAX) DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MAX)
#undef DEFINE_SOC_HWPM_ACTIVE_IP #undef DEFINE_SOC_HWPM_ACTIVE_IP

2
drivers/tegra/hwpm/include/tegra_hwpm.h
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@@ -79,6 +79,7 @@ enum tegra_hwpm_ip_enum {
TEGRA_HWPM_IP_APE, TEGRA_HWPM_IP_APE,
TEGRA_HWPM_IP_C2C, TEGRA_HWPM_IP_C2C,
TEGRA_HWPM_IP_SMMU, TEGRA_HWPM_IP_SMMU,
TEGRA_HWPM_IP_CL2,
TERGA_HWPM_NUM_IPS TERGA_HWPM_NUM_IPS
}; };
@@ -109,6 +110,7 @@ enum tegra_hwpm_resource_enum {
TEGRA_HWPM_RESOURCE_APE, TEGRA_HWPM_RESOURCE_APE,
TEGRA_HWPM_RESOURCE_C2C, TEGRA_HWPM_RESOURCE_C2C,
TEGRA_HWPM_RESOURCE_SMMU, TEGRA_HWPM_RESOURCE_SMMU,
TEGRA_HWPM_RESOURCE_CL2,
TERGA_HWPM_NUM_RESOURCES TERGA_HWPM_NUM_RESOURCES
}; };

6
drivers/tegra/hwpm/os/linux/ip_utils.c
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@@ -93,6 +93,9 @@ static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm,
case TEGRA_SOC_HWPM_IP_SMMU: case TEGRA_SOC_HWPM_IP_SMMU:
ip_enum_idx = TEGRA_HWPM_IP_SMMU; ip_enum_idx = TEGRA_HWPM_IP_SMMU;
break; break;
case TEGRA_SOC_HWPM_IP_CL2:
ip_enum_idx = TEGRA_HWPM_IP_CL2;
break;
default: default:
tegra_hwpm_err(hwpm, tegra_hwpm_err(hwpm,
"Queried enum tegra_soc_hwpm_ip %d is invalid", "Queried enum tegra_soc_hwpm_ip %d is invalid",
@@ -201,6 +204,9 @@ u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm,
case TEGRA_SOC_HWPM_RESOURCE_SMMU: case TEGRA_SOC_HWPM_RESOURCE_SMMU:
res_enum_idx = TEGRA_HWPM_RESOURCE_SMMU; res_enum_idx = TEGRA_HWPM_RESOURCE_SMMU;
break; break;
case TEGRA_SOC_HWPM_RESOURCE_CL2:
res_enum_idx = TEGRA_HWPM_RESOURCE_CL2;
break;
default: default:
tegra_hwpm_err(hwpm, tegra_hwpm_err(hwpm,
"Queried enum tegra_soc_hwpm_resource %d is invalid", "Queried enum tegra_soc_hwpm_resource %d is invalid",

2
include/uapi/linux/tegra-soc-hwpm-uapi.h
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@@ -46,6 +46,7 @@ enum tegra_soc_hwpm_ip {
TEGRA_SOC_HWPM_IP_APE, TEGRA_SOC_HWPM_IP_APE,
TEGRA_SOC_HWPM_IP_C2C, TEGRA_SOC_HWPM_IP_C2C,
TEGRA_SOC_HWPM_IP_SMMU, TEGRA_SOC_HWPM_IP_SMMU,
TEGRA_SOC_HWPM_IP_CL2,
TERGA_SOC_HWPM_NUM_IPS TERGA_SOC_HWPM_NUM_IPS
}; };
@@ -114,6 +115,7 @@ enum tegra_soc_hwpm_resource {
TEGRA_SOC_HWPM_RESOURCE_APE, TEGRA_SOC_HWPM_RESOURCE_APE,
TEGRA_SOC_HWPM_RESOURCE_C2C, TEGRA_SOC_HWPM_RESOURCE_C2C,
TEGRA_SOC_HWPM_RESOURCE_SMMU, TEGRA_SOC_HWPM_RESOURCE_SMMU,
TEGRA_SOC_HWPM_RESOURCE_CL2,
TERGA_SOC_HWPM_NUM_RESOURCES TERGA_SOC_HWPM_NUM_RESOURCES
}; };