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tegra: hwpm: consider PMA as regular IP

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PMA and RTR perfmuxes contain registers required to configure HWPM.
So currently, PMA and RTR IPs are treated as special case and
initialized - released along with the driver.
However, as RTR IP includes both router and pma apertures, only treat
RTR as special IP. Change RTR config to have router and pma apertures
as separate instances. Define macros for router and pma instance index.
This will be allow to retrieve router and pma aperture structures.

Remove PMA IP reservation during driver init and PMA IP release at
driver close. As PMA IP is not treated special now,
remove get_pma_ip_idx() HAL.

Modify HWPM configuration functions to use router and pma apertures
initialized as part of RTR IP.

Jira THWPM-41

Change-Id: Ic82b2d07769c1b5c4601e07776be06087468657d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2706488
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vedashree Vidwans
2022-04-30 23:16:07 -07:00
committed by mobile promotions
parent 25f0737897
commit 7dd5b5c956
12 changed files with 71 additions and 307 deletions
Download Patch File Download Diff File Expand all files Collapse all files

229
common/tegra_hwpm_aperture_utils.c
View File

@@ -147,168 +147,19 @@ int tegra_hwpm_perfmux_release(struct tegra_soc_hwpm *hwpm,
return 0; return 0;
} }
int tegra_hwpm_reserve_pma(struct tegra_soc_hwpm *hwpm)
{
u32 perfmux_idx = 0U, perfmon_idx;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
struct hwpm_ip *chip_ip_pma = NULL;
hwpm_ip_perfmux *pma_perfmux = NULL;
hwpm_ip_perfmon *pma_perfmon = NULL;
int ret = 0, err = 0;
tegra_hwpm_fn(hwpm, " ");
chip_ip_pma = active_chip->chip_ips[active_chip->get_pma_int_idx(hwpm)];
/* Make sure that PMA is not reserved */
if (chip_ip_pma->reserved == true) {
tegra_hwpm_err(hwpm, "PMA already reserved, ignoring");
return 0;
}
/* Reserve PMA perfmux */
for (perfmux_idx = 0U; perfmux_idx < chip_ip_pma->num_perfmux_slots;
perfmux_idx++) {
pma_perfmux = chip_ip_pma->ip_perfmux[perfmux_idx];
if (pma_perfmux == NULL) {
continue;
}
/* Since PMA is hwpm component, use perfmon reserve function */
ret = tegra_hwpm_perfmon_reserve(hwpm, pma_perfmux);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"PMA perfmux %d reserve failed", perfmux_idx);
return ret;
}
chip_ip_pma->fs_mask |= pma_perfmux->hw_inst_mask;
}
/* Reserve PMA perfmons */
for (perfmon_idx = 0U; perfmon_idx < chip_ip_pma->num_perfmon_slots;
perfmon_idx++) {
pma_perfmon = chip_ip_pma->ip_perfmon[perfmon_idx];
if (pma_perfmon == NULL) {
continue;
}
ret = tegra_hwpm_perfmon_reserve(hwpm, pma_perfmon);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"PMA perfmon %d reserve failed", perfmon_idx);
goto fail;
}
}
chip_ip_pma->reserved = true;
return 0;
fail:
for (perfmux_idx = 0U; perfmux_idx < chip_ip_pma->num_perfmux_slots;
perfmux_idx++) {
pma_perfmux = chip_ip_pma->ip_perfmux[perfmux_idx];
if (pma_perfmux == NULL) {
continue;
}
/* Since PMA is hwpm component, use perfmon release function */
err = tegra_hwpm_perfmon_release(hwpm, pma_perfmux);
if (err != 0) {
tegra_hwpm_err(hwpm,
"PMA perfmux %d release failed", perfmux_idx);
}
chip_ip_pma->fs_mask &= ~(pma_perfmux->hw_inst_mask);
}
return ret;
}
int tegra_hwpm_release_pma(struct tegra_soc_hwpm *hwpm)
{
int ret = 0;
u32 perfmux_idx, perfmon_idx;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
struct hwpm_ip *chip_ip_pma = NULL;
hwpm_ip_perfmux *pma_perfmux = NULL;
hwpm_ip_perfmon *pma_perfmon = NULL;
tegra_hwpm_fn(hwpm, " ");
chip_ip_pma = active_chip->chip_ips[active_chip->get_pma_int_idx(hwpm)];
if (!chip_ip_pma->reserved) {
tegra_hwpm_dbg(hwpm, hwpm_info, "PMA wasn't mapped, ignoring.");
return 0;
}
/* Release PMA perfmux */
for (perfmux_idx = 0U; perfmux_idx < chip_ip_pma->num_perfmux_slots;
perfmux_idx++) {
pma_perfmux = chip_ip_pma->ip_perfmux[perfmux_idx];
if (pma_perfmux == NULL) {
continue;
}
/* Since PMA is hwpm component, use perfmon release function */
ret = tegra_hwpm_perfmon_release(hwpm, pma_perfmux);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"PMA perfmux %d release failed", perfmux_idx);
return ret;
}
chip_ip_pma->fs_mask &= ~(pma_perfmux->hw_inst_mask);
}
/* Release PMA perfmons */
for (perfmon_idx = 0U; perfmon_idx < chip_ip_pma->num_perfmon_slots;
perfmon_idx++) {
pma_perfmon = chip_ip_pma->ip_perfmon[perfmon_idx];
if (pma_perfmon == NULL) {
continue;
}
ret = tegra_hwpm_perfmon_release(hwpm, pma_perfmon);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"PMA perfmon %d release failed", perfmon_idx);
return ret;
}
}
chip_ip_pma->reserved = false;
return 0;
}
int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm) int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm)
{ {
int ret = 0; int ret = 0;
u32 perfmux_idx = 0U, perfmon_idx; u32 perfmux_idx = 0U;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
struct hwpm_ip *chip_ip_rtr = NULL; struct hwpm_ip *chip_ip_rtr = NULL;
struct hwpm_ip *chip_ip_pma = NULL;
hwpm_ip_perfmux *pma_perfmux = NULL;
hwpm_ip_perfmux *rtr_perfmux = NULL; hwpm_ip_perfmux *rtr_perfmux = NULL;
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
chip_ip_pma = active_chip->chip_ips[active_chip->get_pma_int_idx(hwpm)];
chip_ip_rtr = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)]; chip_ip_rtr = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)];
/* Currently, PMA has only one perfmux */
pma_perfmux = &chip_ip_pma->perfmux_static_array[0U];
/* Verify that PMA is reserved before RTR */ /* Make sure that RTR is not already reserved */
if (chip_ip_pma->reserved == false) {
tegra_hwpm_err(hwpm, "PMA should be reserved before RTR");
return -EINVAL;
}
/* Make sure that RTR is not reserved */
if (chip_ip_rtr->reserved == true) { if (chip_ip_rtr->reserved == true) {
tegra_hwpm_err(hwpm, "RTR already reserved, ignoring"); tegra_hwpm_err(hwpm, "RTR already reserved, ignoring");
return 0; return 0;
@@ -323,34 +174,19 @@ int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm)
continue; continue;
} }
if (rtr_perfmux->start_abs_pa == pma_perfmux->start_abs_pa) { /* Since RTR is hwpm component, use perfmon reserve function */
/* This is PMA perfmux wrt RTR aperture */ ret = tegra_hwpm_perfmon_reserve(hwpm, rtr_perfmux);
rtr_perfmux->start_pa = pma_perfmux->start_pa; if (ret != 0) {
rtr_perfmux->end_pa = pma_perfmux->end_pa; tegra_hwpm_err(hwpm,
rtr_perfmux->dt_mmio = pma_perfmux->dt_mmio; "RTR perfmux %d reserve failed",
if (hwpm->fake_registers_enabled) { perfmux_idx);
rtr_perfmux->fake_registers = return ret;
pma_perfmux->fake_registers;
}
} else {
/* Since RTR is hwpm component,
* use perfmon reserve function */
ret = tegra_hwpm_perfmon_reserve(hwpm, rtr_perfmux);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"RTR perfmux %d reserve failed",
perfmux_idx);
return ret;
}
} }
chip_ip_rtr->fs_mask |= rtr_perfmux->hw_inst_mask; chip_ip_rtr->fs_mask |= rtr_perfmux->hw_inst_mask;
} }
/* Reserve RTR perfmons */ /* No perfmons in RTR */
for (perfmon_idx = 0U; perfmon_idx < chip_ip_rtr->num_perfmon_slots;
perfmon_idx++) {
/* No perfmons in RTR */
}
chip_ip_rtr->reserved = true; chip_ip_rtr->reserved = true;
@@ -360,25 +196,14 @@ int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm)
int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm) int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm)
{ {
int ret = 0; int ret = 0;
u32 perfmux_idx, perfmon_idx; u32 perfmux_idx;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
struct hwpm_ip *chip_ip_rtr = NULL; struct hwpm_ip *chip_ip_rtr = NULL;
struct hwpm_ip *chip_ip_pma = NULL;
hwpm_ip_perfmux *pma_perfmux = NULL;
hwpm_ip_perfmux *rtr_perfmux = NULL; hwpm_ip_perfmux *rtr_perfmux = NULL;
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
chip_ip_pma = active_chip->chip_ips[active_chip->get_pma_int_idx(hwpm)];
chip_ip_rtr = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)]; chip_ip_rtr = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)];
/* Currently, PMA has only one perfmux */
pma_perfmux = &chip_ip_pma->perfmux_static_array[0U];
/* Verify that PMA isn't released before RTR */
if (chip_ip_pma->reserved == false) {
tegra_hwpm_err(hwpm, "PMA shouldn't be released before RTR");
return -EINVAL;
}
if (!chip_ip_rtr->reserved) { if (!chip_ip_rtr->reserved) {
tegra_hwpm_dbg(hwpm, hwpm_info, "RTR wasn't mapped, ignoring."); tegra_hwpm_dbg(hwpm, hwpm_info, "RTR wasn't mapped, ignoring.");
@@ -394,32 +219,18 @@ int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm)
continue; continue;
} }
if (rtr_perfmux->start_abs_pa == pma_perfmux->start_abs_pa) { /* RTR is hwpm component, use perfmon release func */
/* This is PMA perfmux wrt RTR aperture */ ret = tegra_hwpm_perfmon_release(hwpm, rtr_perfmux);
rtr_perfmux->start_pa = 0ULL; if (ret != 0) {
rtr_perfmux->end_pa = 0ULL; tegra_hwpm_err(hwpm, "RTR perfmux %d release failed",
rtr_perfmux->dt_mmio = NULL; perfmux_idx);
if (hwpm->fake_registers_enabled) { return ret;
rtr_perfmux->fake_registers = NULL;
}
} else {
/* RTR is hwpm component, use perfmon release func */
ret = tegra_hwpm_perfmon_release(hwpm, rtr_perfmux);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"RTR perfmux %d release failed",
perfmux_idx);
return ret;
}
} }
chip_ip_rtr->fs_mask &= ~(rtr_perfmux->hw_inst_mask); chip_ip_rtr->fs_mask &= ~(rtr_perfmux->hw_inst_mask);
} }
/* Release RTR perfmon */ /* No perfmons in RTR */
for (perfmon_idx = 0U; perfmon_idx < chip_ip_rtr->num_perfmon_slots;
perfmon_idx++) {
/* No RTR perfmons */
}
chip_ip_rtr->reserved = false; chip_ip_rtr->reserved = false;
return 0; return 0;

20
common/tegra_hwpm_init.c
View File

@@ -139,17 +139,11 @@ int tegra_hwpm_setup_hw(struct tegra_soc_hwpm *hwpm)
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
/* /*
* Map PMA and RTR apertures * Map RTR aperture
* PMA and RTR are hwpm apertures which include hwpm config registers. * RTR is hwpm aperture which includes hwpm config registers.
* Map/reserve these apertures to get MMIO address required for hwpm * Map/reserve these apertures to get MMIO address required for hwpm
* configuration (following steps). * configuration (following steps).
*/ */
ret = hwpm->active_chip->reserve_pma(hwpm);
if (ret < 0) {
tegra_hwpm_err(hwpm, "Unable to reserve PMA aperture");
goto fail;
}
ret = hwpm->active_chip->reserve_rtr(hwpm); ret = hwpm->active_chip->reserve_rtr(hwpm);
if (ret < 0) { if (ret < 0) {
tegra_hwpm_err(hwpm, "Unable to reserve RTR aperture"); tegra_hwpm_err(hwpm, "Unable to reserve RTR aperture");
@@ -196,8 +190,8 @@ int tegra_hwpm_release_hw(struct tegra_soc_hwpm *hwpm)
} }
/* /*
* Unmap PMA and RTR apertures * Unmap RTR apertures
* Since, PMA and RTR hwpm apertures consist of hwpm config registers, * Since, RTR hwpm apertures consist of hwpm config registers,
* these aperture mappings are required to reset hwpm config. * these aperture mappings are required to reset hwpm config.
* Hence, explicitly unmap/release these apertures as a last step. * Hence, explicitly unmap/release these apertures as a last step.
*/ */
@@ -207,12 +201,6 @@ int tegra_hwpm_release_hw(struct tegra_soc_hwpm *hwpm)
goto fail; goto fail;
} }
ret = hwpm->active_chip->release_pma(hwpm);
if (ret < 0) {
tegra_hwpm_err(hwpm, "Unable to release PMA aperture");
goto fail;
}
return 0; return 0;
fail: fail:
return ret; return ret;

7
common/tegra_hwpm_resource_utils.c
View File

@@ -337,8 +337,7 @@ int tegra_hwpm_func_single_ip(struct tegra_soc_hwpm *hwpm,
break; break;
case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE: case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE:
/* PMA and RTR are already reserved */ /* PMA and RTR are already reserved */
if ((ip_idx == active_chip->get_pma_int_idx(hwpm)) || if (ip_idx == active_chip->get_rtr_int_idx(hwpm)) {
(ip_idx == active_chip->get_rtr_int_idx(hwpm))) {
return 0; return 0;
} }
/* Skip IPs which are already reserved */ /* Skip IPs which are already reserved */
@@ -354,11 +353,11 @@ int tegra_hwpm_func_single_ip(struct tegra_soc_hwpm *hwpm,
"Chip IP %d not available", ip_idx); "Chip IP %d not available", ip_idx);
return 0; return 0;
} }
break; break;
case TEGRA_HWPM_RELEASE_RESOURCES: case TEGRA_HWPM_RELEASE_RESOURCES:
/* PMA and RTR will be released later */ /* PMA and RTR will be released later */
if ((ip_idx == active_chip->get_pma_int_idx(hwpm)) || if (ip_idx == active_chip->get_rtr_int_idx(hwpm)) {
(ip_idx == active_chip->get_rtr_int_idx(hwpm))) {
return 0; return 0;
} }
/* Skip unavailable IPs */ /* Skip unavailable IPs */

2
hal/t234/ip/pma/t234_hwpm_ip_pma.c
View File

@@ -85,7 +85,7 @@ struct hwpm_ip t234_hwpm_ip_pma = {
.ip_perfmux = NULL, .ip_perfmux = NULL,
.override_enable = false, .override_enable = false,
.fs_mask = 0U, .fs_mask = 0x1U,
.perfmon_static_array = t234_pma_perfmon_static_array, .perfmon_static_array = t234_pma_perfmon_static_array,
.perfmux_static_array = t234_pma_perfmux_static_array, .perfmux_static_array = t234_pma_perfmux_static_array,
.reserved = false, .reserved = false,

10
hal/t234/ip/rtr/t234_hwpm_ip_rtr.h
View File

@@ -17,9 +17,15 @@
#define T234_HWPM_ACTIVE_IP_RTR T234_HWPM_IP_RTR #define T234_HWPM_ACTIVE_IP_RTR T234_HWPM_IP_RTR
/* This data should ideally be available in HW headers */ /* This data should ideally be available in HW headers */
#define T234_HWPM_IP_RTR_NUM_INSTANCES 1U #define T234_HWPM_IP_RTR_NUM_INSTANCES 2U
#define T234_HWPM_IP_RTR_NUM_PERFMON_PER_INST 0U #define T234_HWPM_IP_RTR_NUM_PERFMON_PER_INST 0U
#define T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST 2U #define T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST 1U
#define T234_HWPM_IP_RTR_STATIC_INDEX_RTR \
((1U * T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST) - 1U)
#define T234_HWPM_IP_RTR_STATIC_INDEX_PMA \
((2U * T234_HWPM_IP_RTR_NUM_PERFMUX_PER_INST) - 1U)
extern struct hwpm_ip t234_hwpm_ip_rtr; extern struct hwpm_ip t234_hwpm_ip_rtr;

2
hal/t234/ip/scf/t234_hwpm_ip_scf.c
View File

@@ -66,7 +66,7 @@ struct hwpm_ip t234_hwpm_ip_scf = {
.ip_perfmux = NULL, .ip_perfmux = NULL,
.override_enable = false, .override_enable = false,
.fs_mask = 0U, .fs_mask = 0x1U,
.perfmon_static_array = t234_scf_perfmon_static_array, .perfmon_static_array = t234_scf_perfmon_static_array,
.perfmux_static_array = t234_scf_perfmux_static_array, .perfmux_static_array = t234_scf_perfmux_static_array,
.reserved = false, .reserved = false,

45
hal/t234/t234_hwpm_aperture_utils.c
View File

@@ -37,12 +37,12 @@ int t234_hwpm_disable_triggers(struct tegra_soc_hwpm *hwpm)
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
/* Currently, PMA has only one perfmux */
pma_perfmux = &active_chip->chip_ips[
active_chip->get_pma_int_idx(hwpm)]->perfmux_static_array[0U];
/* Currently, RTR specific perfmux is added at index 0 */
rtr_perfmux = &active_chip->chip_ips[ rtr_perfmux = &active_chip->chip_ips[
active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[0U]; active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_RTR];
pma_perfmux = &active_chip->chip_ips[
active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
/* Disable PMA triggers */ /* Disable PMA triggers */
reg_val = tegra_hwpm_readl(hwpm, pma_perfmux, reg_val = tegra_hwpm_readl(hwpm, pma_perfmux,
@@ -99,7 +99,8 @@ int t234_hwpm_init_prod_values(struct tegra_soc_hwpm *hwpm)
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
/* Currently, PMA has only one perfmux */ /* Currently, PMA has only one perfmux */
hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[
active_chip->get_pma_int_idx(hwpm)]->perfmux_static_array[0U]; active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
@@ -126,7 +127,7 @@ int t234_hwpm_disable_slcg(struct tegra_soc_hwpm *hwpm)
u32 field_val = 0U; u32 field_val = 0U;
u32 reg_val = 0U; u32 reg_val = 0U;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
struct hwpm_ip *pma_ip = NULL, *rtr_ip = NULL; struct hwpm_ip *rtr_ip = NULL;
hwpm_ip_perfmux *pma_perfmux = NULL; hwpm_ip_perfmux *pma_perfmux = NULL;
hwpm_ip_perfmux *rtr_perfmux = NULL; hwpm_ip_perfmux *rtr_perfmux = NULL;
@@ -136,23 +137,17 @@ int t234_hwpm_disable_slcg(struct tegra_soc_hwpm *hwpm)
return -ENODEV; return -ENODEV;
} }
pma_ip = active_chip->chip_ips[active_chip->get_pma_int_idx(hwpm)];
rtr_ip = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)]; rtr_ip = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)];
if ((pma_ip == NULL) || !(pma_ip->reserved)) {
tegra_hwpm_err(hwpm, "PMA uninitialized");
return -ENODEV;
}
if ((rtr_ip == NULL) || !(rtr_ip->reserved)) { if ((rtr_ip == NULL) || !(rtr_ip->reserved)) {
tegra_hwpm_err(hwpm, "RTR uninitialized"); tegra_hwpm_err(hwpm, "RTR uninitialized");
return -ENODEV; return -ENODEV;
} }
/* Currently, PMA has only one perfmux */ pma_perfmux = &rtr_ip->perfmux_static_array[
pma_perfmux = &pma_ip->perfmux_static_array[0U]; T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
/* Currently, RTR specific perfmux is added at index 0 */ rtr_perfmux = &rtr_ip->perfmux_static_array[
rtr_perfmux = &rtr_ip->perfmux_static_array[0U]; T234_HWPM_IP_RTR_STATIC_INDEX_RTR];
reg_val = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r()); reg_val = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r());
reg_val = set_field(reg_val, pmasys_cg2_slcg_m(), reg_val = set_field(reg_val, pmasys_cg2_slcg_m(),
@@ -180,7 +175,7 @@ int t234_hwpm_enable_slcg(struct tegra_soc_hwpm *hwpm)
u32 field_mask = 0U; u32 field_mask = 0U;
u32 field_val = 0U; u32 field_val = 0U;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
struct hwpm_ip *pma_ip = NULL, *rtr_ip = NULL; struct hwpm_ip *rtr_ip = NULL;
hwpm_ip_perfmux *pma_perfmux = NULL; hwpm_ip_perfmux *pma_perfmux = NULL;
hwpm_ip_perfmux *rtr_perfmux = NULL; hwpm_ip_perfmux *rtr_perfmux = NULL;
@@ -190,23 +185,17 @@ int t234_hwpm_enable_slcg(struct tegra_soc_hwpm *hwpm)
return -ENODEV; return -ENODEV;
} }
pma_ip = active_chip->chip_ips[active_chip->get_pma_int_idx(hwpm)];
rtr_ip = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)]; rtr_ip = active_chip->chip_ips[active_chip->get_rtr_int_idx(hwpm)];
if ((pma_ip == NULL) || !(pma_ip->reserved)) {
tegra_hwpm_err(hwpm, "PMA uninitialized");
return -ENODEV;
}
if ((rtr_ip == NULL) || !(rtr_ip->reserved)) { if ((rtr_ip == NULL) || !(rtr_ip->reserved)) {
tegra_hwpm_err(hwpm, "RTR uninitialized"); tegra_hwpm_err(hwpm, "RTR uninitialized");
return -ENODEV; return -ENODEV;
} }
/* Currently, PMA has only one perfmux */ pma_perfmux = &rtr_ip->perfmux_static_array[
pma_perfmux = &pma_ip->perfmux_static_array[0U]; T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
/* Currently, RTR specific perfmux is added at index 0 */ rtr_perfmux = &rtr_ip->perfmux_static_array[
rtr_perfmux = &rtr_ip->perfmux_static_array[0U]; T234_HWPM_IP_RTR_STATIC_INDEX_RTR];
reg_val = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r()); reg_val = tegra_hwpm_readl(hwpm, pma_perfmux, pmasys_cg2_r());
reg_val = set_field(reg_val, pmasys_cg2_slcg_m(), reg_val = set_field(reg_val, pmasys_cg2_slcg_m(),

23
hal/t234/t234_hwpm_interface_utils.c
View File

@@ -28,7 +28,6 @@ struct tegra_soc_hwpm_chip t234_chip_info = {
.is_ip_active = t234_hwpm_is_ip_active, .is_ip_active = t234_hwpm_is_ip_active,
.is_resource_active = t234_hwpm_is_resource_active, .is_resource_active = t234_hwpm_is_resource_active,
.get_pma_int_idx = t234_get_pma_int_idx,
.get_rtr_int_idx = t234_get_rtr_int_idx, .get_rtr_int_idx = t234_get_rtr_int_idx,
.get_ip_max_idx = t234_get_ip_max_idx, .get_ip_max_idx = t234_get_ip_max_idx,
@@ -42,9 +41,7 @@ struct tegra_soc_hwpm_chip t234_chip_info = {
.disable_slcg = t234_hwpm_disable_slcg, .disable_slcg = t234_hwpm_disable_slcg,
.enable_slcg = t234_hwpm_enable_slcg, .enable_slcg = t234_hwpm_enable_slcg,
.reserve_pma = tegra_hwpm_reserve_pma,
.reserve_rtr = tegra_hwpm_reserve_rtr, .reserve_rtr = tegra_hwpm_reserve_rtr,
.release_pma = tegra_hwpm_release_pma,
.release_rtr = tegra_hwpm_release_rtr, .release_rtr = tegra_hwpm_release_rtr,
.perfmon_enable = t234_hwpm_perfmon_enable, .perfmon_enable = t234_hwpm_perfmon_enable,
@@ -83,11 +80,6 @@ static bool t234_hwpm_validate_hals(struct tegra_soc_hwpm *hwpm)
return false; return false;
} }
if (hwpm->active_chip->get_pma_int_idx == NULL) {
tegra_hwpm_err(hwpm, "get_pma_int_idx HAL uninitialized");
return false;
}
if (hwpm->active_chip->get_rtr_int_idx == NULL) { if (hwpm->active_chip->get_rtr_int_idx == NULL) {
tegra_hwpm_err(hwpm, "get_rtr_int_idx HAL uninitialized"); tegra_hwpm_err(hwpm, "get_rtr_int_idx HAL uninitialized");
return false; return false;
@@ -133,21 +125,11 @@ static bool t234_hwpm_validate_hals(struct tegra_soc_hwpm *hwpm)
return false; return false;
} }
if (hwpm->active_chip->reserve_pma == NULL) {
tegra_hwpm_err(hwpm, "reserve_pma uninitialized");
return false;
}
if (hwpm->active_chip->reserve_rtr == NULL) { if (hwpm->active_chip->reserve_rtr == NULL) {
tegra_hwpm_err(hwpm, "reserve_rtr uninitialized"); tegra_hwpm_err(hwpm, "reserve_rtr uninitialized");
return false; return false;
} }
if (hwpm->active_chip->release_pma == NULL) {
tegra_hwpm_err(hwpm, "release_pma uninitialized");
return false;
}
if (hwpm->active_chip->release_rtr == NULL) { if (hwpm->active_chip->release_rtr == NULL) {
tegra_hwpm_err(hwpm, "release_rtr uninitialized"); tegra_hwpm_err(hwpm, "release_rtr uninitialized");
return false; return false;
@@ -444,11 +426,6 @@ bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
return (config_ip != TEGRA_SOC_HWPM_IP_INACTIVE); return (config_ip != TEGRA_SOC_HWPM_IP_INACTIVE);
} }
u32 t234_get_pma_int_idx(struct tegra_soc_hwpm *hwpm)
{
return T234_HWPM_IP_PMA;
}
u32 t234_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm) u32 t234_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm)
{ {
return T234_HWPM_IP_RTR; return T234_HWPM_IP_RTR;

3
hal/t234/t234_hwpm_internal.h
View File

@@ -36,8 +36,8 @@
#define T234_HWPM_ACTIVE_IP_MAX T234_HWPM_IP_MAX #define T234_HWPM_ACTIVE_IP_MAX T234_HWPM_IP_MAX
#define T234_ACTIVE_IPS \ #define T234_ACTIVE_IPS \
DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_PMA), \
DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_RTR), \ DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_RTR), \
DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_PMA), \
DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_VI), \ DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_VI), \
DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_ISP), \ DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_ISP), \
DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_VIC), \ DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_VIC), \
@@ -73,7 +73,6 @@ bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm, bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
u32 res_index, u32 *config_ip_index); u32 res_index, u32 *config_ip_index);
u32 t234_get_pma_int_idx(struct tegra_soc_hwpm *hwpm);
u32 t234_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm); u32 t234_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm);
u32 t234_get_ip_max_idx(struct tegra_soc_hwpm *hwpm); u32 t234_get_ip_max_idx(struct tegra_soc_hwpm *hwpm);

32
hal/t234/t234_hwpm_mem_buf_utils.c
View File

@@ -26,9 +26,9 @@
int t234_hwpm_disable_mem_mgmt(struct tegra_soc_hwpm *hwpm) int t234_hwpm_disable_mem_mgmt(struct tegra_soc_hwpm *hwpm)
{ {
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
/* Currently, PMA has only one perfmux */
hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[
active_chip->get_pma_int_idx(hwpm)]->perfmux_static_array[0U]; active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
@@ -50,9 +50,9 @@ int t234_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm,
u32 outsize = 0; u32 outsize = 0;
u32 mem_bytes_addr = 0; u32 mem_bytes_addr = 0;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
/* Currently, PMA has only one perfmux */
hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[
active_chip->get_pma_int_idx(hwpm)]->perfmux_static_array[0U]; active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
@@ -91,9 +91,9 @@ int t234_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm,
int t234_hwpm_invalidate_mem_config(struct tegra_soc_hwpm *hwpm) int t234_hwpm_invalidate_mem_config(struct tegra_soc_hwpm *hwpm)
{ {
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
/* Currently, PMA has only one perfmux */
hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[
active_chip->get_pma_int_idx(hwpm)]->perfmux_static_array[0U]; active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
@@ -109,9 +109,9 @@ int t234_hwpm_stream_mem_bytes(struct tegra_soc_hwpm *hwpm)
u32 reg_val = 0U; u32 reg_val = 0U;
u32 *mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_bytes_kernel); u32 *mem_bytes_kernel_u32 = (u32 *)(hwpm->mem_bytes_kernel);
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
/* Currently, PMA has only one perfmux */
hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[
active_chip->get_pma_int_idx(hwpm)]->perfmux_static_array[0U]; active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
@@ -132,9 +132,9 @@ int t234_hwpm_disable_pma_streaming(struct tegra_soc_hwpm *hwpm)
{ {
u32 reg_val = 0U; u32 reg_val = 0U;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
/* Currently, PMA has only one perfmux */
hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[
active_chip->get_pma_int_idx(hwpm)]->perfmux_static_array[0U]; active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
@@ -162,9 +162,9 @@ int t234_hwpm_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm,
u64 mem_bump) u64 mem_bump)
{ {
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
/* Currently, PMA has only one perfmux */
hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[
active_chip->get_pma_int_idx(hwpm)]->perfmux_static_array[0U]; active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
@@ -182,9 +182,9 @@ int t234_hwpm_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm,
u64 t234_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm) u64 t234_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm)
{ {
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
/* Currently, PMA has only one perfmux */
hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[
active_chip->get_pma_int_idx(hwpm)]->perfmux_static_array[0U]; active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");
@@ -196,9 +196,9 @@ bool t234_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm)
{ {
u32 reg_val, field_val; u32 reg_val, field_val;
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip; struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
/* Currently, PMA has only one perfmux */
hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[ hwpm_ip_perfmux *pma_perfmux = &active_chip->chip_ips[
active_chip->get_pma_int_idx(hwpm)]->perfmux_static_array[0U]; active_chip->get_rtr_int_idx(hwpm)]->perfmux_static_array[
T234_HWPM_IP_RTR_STATIC_INDEX_PMA];
tegra_hwpm_fn(hwpm, " "); tegra_hwpm_fn(hwpm, " ");

3
include/tegra_hwpm.h
View File

@@ -232,7 +232,6 @@ struct tegra_soc_hwpm_chip {
bool (*is_resource_active)(struct tegra_soc_hwpm *hwpm, bool (*is_resource_active)(struct tegra_soc_hwpm *hwpm,
u32 res_index, u32 *config_ip_index); u32 res_index, u32 *config_ip_index);
u32 (*get_pma_int_idx)(struct tegra_soc_hwpm *hwpm);
u32 (*get_rtr_int_idx)(struct tegra_soc_hwpm *hwpm); u32 (*get_rtr_int_idx)(struct tegra_soc_hwpm *hwpm);
u32 (*get_ip_max_idx)(struct tegra_soc_hwpm *hwpm); u32 (*get_ip_max_idx)(struct tegra_soc_hwpm *hwpm);
@@ -248,9 +247,7 @@ struct tegra_soc_hwpm_chip {
int (*disable_slcg)(struct tegra_soc_hwpm *hwpm); int (*disable_slcg)(struct tegra_soc_hwpm *hwpm);
int (*enable_slcg)(struct tegra_soc_hwpm *hwpm); int (*enable_slcg)(struct tegra_soc_hwpm *hwpm);
int (*reserve_pma)(struct tegra_soc_hwpm *hwpm);
int (*reserve_rtr)(struct tegra_soc_hwpm *hwpm); int (*reserve_rtr)(struct tegra_soc_hwpm *hwpm);
int (*release_pma)(struct tegra_soc_hwpm *hwpm);
int (*release_rtr)(struct tegra_soc_hwpm *hwpm); int (*release_rtr)(struct tegra_soc_hwpm *hwpm);
int (*disable_triggers)(struct tegra_soc_hwpm *hwpm); int (*disable_triggers)(struct tegra_soc_hwpm *hwpm);

2
include/tegra_hwpm_common.h
View File

@@ -56,9 +56,7 @@ int tegra_hwpm_reserve_resource(struct tegra_soc_hwpm *hwpm, u32 resource);
int tegra_hwpm_release_resources(struct tegra_soc_hwpm *hwpm); int tegra_hwpm_release_resources(struct tegra_soc_hwpm *hwpm);
int tegra_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm); int tegra_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm);
int tegra_hwpm_reserve_pma(struct tegra_soc_hwpm *hwpm);
int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm); int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm);
int tegra_hwpm_release_pma(struct tegra_soc_hwpm *hwpm);
int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm); int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm);
int tegra_hwpm_perfmon_reserve(struct tegra_soc_hwpm *hwpm, int tegra_hwpm_perfmon_reserve(struct tegra_soc_hwpm *hwpm,