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tegra: soc_hwpm: enable available IPs for Si

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Enable below IPs for HWPM on Si
- ISP
- VIC
- OFA
- PVA
- NVDLA
- SCF
- NVDEC
- NVENC
- MSS *

Change-Id: Id35cb48ac5447e5b54ff9066a6f38e3f45e103bf
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2601361
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2021-10-15 11:19:41 -07:00
committed by mobile promotions
parent 08cf289cbd
commit 8c4e714e52
1 changed files with 10 additions and 6 deletions
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16
tegra-soc-hwpm-ioctl.c
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@@ -1164,16 +1164,20 @@ static int tegra_soc_hwpm_open(struct inode *inode, struct file *filp)
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_NVLINK] = 0x1;
}
if (tegra_platform_is_silicon()) {
/* Update fs_info once IP is validated */
/* Static IP instances corresponding to silicon */
// hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_VI] = 0x3;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_ISP] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_VIC] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_OFA] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_PVA] = 0x1;
/*
* Bug 3362415: MSS Channel cannot be force enabled on TOT
* Mark MSS channels as floorswept.
*/
/* hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_CHANNEL] = 0xFFFF; */
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_NVDLA] = 0x3;
// hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MGBE] = 0xF;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_SCF] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_NVDEC] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_NVENC] = 0x1;
// hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_PCIE] = 0x32;
// hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_DISPLAY] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_CHANNEL] = 0xFFFF;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_GPU_HUB] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS] = 0x1;
hwpm->ip_fs_info[TEGRA_SOC_HWPM_IP_MSS_MCF] = 0x1;