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tegra: hwpm: t264: Enable VI and ISP compilation

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Enable Camera (VI and ISP) IP file compilation
in HWPM driver for AV+L builds only.

Bug 4345706

Signed-off-by: vasukis <vasukis@nvidia.com>
Change-Id: If647e7e25ce7d1a853cc7c298780538e03392ec0
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3283197
Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Yifei Wan <ywan@nvidia.com>
This commit is contained in:
vasukis
2025-01-14 04:08:46 +00:00
committed by mobile promotions
parent d9ed3fd02b
commit 98c51d644b
4 changed files with 49 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/tegra/hwpm/Makefile.t264.sources
View File

@@ -1,6 +1,6 @@
# -*- mode: makefile -*- # -*- mode: makefile -*-
# #
# Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. # Copyright (c) 2023-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
# #
# Permission is hereby granted, free of charge, to any person obtaining a # Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"), # copy of this software and associated documentation files (the "Software"),
@@ -88,4 +88,10 @@ nvhwpm-t264-objs += hal/t264/ip/ucf_csw/t264_ucf_csw.o
ccflags-y += -DCONFIG_T264_HWPM_IP_CPU ccflags-y += -DCONFIG_T264_HWPM_IP_CPU
nvhwpm-t264-objs += hal/t264/ip/cpu/t264_cpu.o nvhwpm-t264-objs += hal/t264/ip/cpu/t264_cpu.o
ccflags-y += -DCONFIG_T264_HWPM_IP_VI
nvhwpm-t264-objs += hal/t264/ip/vi/t264_vi.o
ccflags-y += -DCONFIG_T264_HWPM_IP_ISP
nvhwpm-t264-objs += hal/t264/ip/isp/t264_isp.o
endif endif

32
drivers/tegra/hwpm/hal/t264/t264_ip.c
View File

@@ -80,12 +80,6 @@ int t264_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
#endif #endif
#if defined(CONFIG_T264_HWPM_IP_CPU) #if defined(CONFIG_T264_HWPM_IP_CPU)
case T264_HWPM_IP_CPU: case T264_HWPM_IP_CPU:
#endif
#if defined(CONFIG_T264_HWPM_IP_VI)
case T264_HWPM_IP_VI:
#endif
#if defined(CONFIG_T264_HWPM_IP_ISP)
case T264_HWPM_IP_ISP:
#endif #endif
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops, ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
base_address, ip_idx, available); base_address, ip_idx, available);
@@ -97,6 +91,32 @@ int t264_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
goto fail; goto fail;
} }
break; break;
#if defined(CONFIG_T264_HWPM_IP_VI)
case T264_HWPM_IP_VI:
#endif
#if defined(CONFIG_T264_HWPM_IP_ISP)
case T264_HWPM_IP_ISP:
#endif
if (tegra_hwpm_is_hypervisor_mode()) {
/*
* VI and ISP are enabled only on AV+L configuration
* as the camera driver is not supported on L4T.
*/
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
base_address, ip_idx, available);
if (ret != 0) {
tegra_hwpm_err(hwpm,
"Failed to %s fs/ops for IP %d (base 0x%llx)",
available == true ? "set" : "reset",
ip_idx, (unsigned long long)base_address);
goto fail;
}
} else {
tegra_hwpm_err(hwpm, "Invalid IP %d for ip_ops", ip_idx);
}
break;
#if defined(CONFIG_T264_HWPM_IP_MSS_CHANNEL) #if defined(CONFIG_T264_HWPM_IP_MSS_CHANNEL)
case T264_HWPM_IP_MSS_CHANNEL: case T264_HWPM_IP_MSS_CHANNEL:
#endif #endif

18
drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: MIT // SPDX-License-Identifier: MIT
/* /*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -224,10 +224,18 @@ struct allowlist t264_cpucore_alist[4] = {
{0x00000018, true}, {0x00000018, true},
}; };
struct allowlist t264_vi_alist[1] = { struct allowlist t264_vi_alist[5] = {
{0x0000c004, true}, {0x00030008, true},
{0x0003000c, true},
{0x00030010, true},
{0x00030014, true},
{0x00030018, true},
}; };
struct allowlist t264_isp_alist[1] = { struct allowlist t264_isp_alist[5] = {
{0x0000c004, true}, {0x00030008, true},
{0x0003000c, true},
{0x00030010, true},
{0x00030014, true},
{0x00030018, true},
}; };

6
drivers/tegra/hwpm/hal/t264/t264_regops_allowlist.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: MIT */ /* SPDX-License-Identifier: MIT */
/* /*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -43,7 +43,7 @@ extern struct allowlist t264_ucf_msw_slc_alist[1];
extern struct allowlist t264_ucf_psn_psw_alist[2]; extern struct allowlist t264_ucf_psn_psw_alist[2];
extern struct allowlist t264_ucf_csw_alist[2]; extern struct allowlist t264_ucf_csw_alist[2];
extern struct allowlist t264_cpucore_alist[4]; extern struct allowlist t264_cpucore_alist[4];
extern struct allowlist t264_vi_alist[1]; extern struct allowlist t264_vi_alist[5];
extern struct allowlist t264_isp_alist[1]; extern struct allowlist t264_isp_alist[5];
#endif /* T264_HWPM_REGOPS_ALLOWLIST_H */ #endif /* T264_HWPM_REGOPS_ALLOWLIST_H */